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PilotTM Motion Processor
MC3510 Single Chip Technical Specifications
for Stepping Motion Control
Performance Motion Devices, Inc. 55 Old Bedford Road Lincoln, MA 01773
Revision 1.1, July 2003
NOTICE
This document contains proprietary and confidential information of Performance Motion Devices, Inc., and is protected by federal copyright law. The contents of this document may not be disclosed to third parties, translated, copied, or duplicated in any form, in whole or in part, without the express written permission of PMD. The information contained in this document is subject to change without notice. No part of this document may be reproduced or transmitted in any form, by any means, electronic or mechanical, for any purpose, without the express written permission of PMD. Copyright 2000 by Performance Motion Devices, Inc. Navigator, Pilot and C-Motion are trademarks of Performance Motion Devices, Inc
Warranty
PMD warrants performance of its products to the specifications applicable at the time of sale in accordance with PMD's standard warranty. Testing and other quality control techniques are utilized to the extent PMD deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Performance Motion Devices, Inc. (PMD) reserves the right to make changes to its products or to discontinue any product or service without notice, and advises customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
Safety Notice
Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage. Products are not designed, authorized, or warranted to be suitable for use in life support devices or systems or other critical applications. Inclusion of PMD products in such applications is understood to be fully at the customer's risk. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent procedural hazards.
Disclaimer
PMD assumes no liability for applications assistance or customer product design. PMD does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of PMD covering or relating to any combination, machine, or process in which such products or services might be or are used. PMD's publication of information regarding any third party's products or services does not constitute PMD's approval, warranty or endorsement thereof.
MC3510 Technical Specifications iii
MC3510 Technical Specifications iv
Related Documents
Pilot Motion Processor User's Guide (MC3000UG) How to set up and use all members of the Pilot Motion Processor family. Pilot Motion Processor Programmer's Reference (MC3000PR) Descriptions of all Pilot Motion Processor commands, with coding syntax and examples, listed alphabetically for quick reference. Pilot Motion Processor Technical Specifications These booklets contain physical and electrical characteristics, timing diagrams, pinouts and pin descriptions of each: MC3110, for brushed servo motion control (MC3110TS) MC3310, for brushless servo motion control (MC3310TS) MC3410, for microstepping motion control (MC3410TS) MC3510, for stepper motion control (MC3510TS) Pilot Motion Processor Developer's Kit Manual (DK3000M) How to install and configure the DK3510 developer's kit PC board.
MC3510 Technical Specifications v
MC3510 Technical Specifications vi
Table of Contents
Warranty...................................................................................................................................................... iii Safety Notice ................................................................................................................................................ iii Disclaimer..................................................................................................................................................... iii Related Documents....................................................................................................................................... v Table of Contents........................................................................................................................................ vii 1 The Pilot Family ........................................................................................................................................ 9 2 Functional Characteristics...................................................................................................................... 11 2.1 Configurations, parameters, and performance .............................................................................. 11 2.2 Physical characteristics and mounting dimensions....................................................................... 13 2.3 Environmental and electrical ratings ............................................................................................ 14 2.4 System configuration.................................................................................................................... 14 2.5 Peripheral device address mapping............................................................................................... 15 3 Electrical Characteristics........................................................................................................................ 16 3.1 DC characteristics......................................................................................................................... 16 3.2 AC characteristics......................................................................................................................... 16 4 I/O Timing Diagrams .............................................................................................................................. 18 4.1 Clock ............................................................................................................................................ 18 4.2 Quadrature encoder input ............................................................................................................. 18 4.3 Reset ............................................................................................................................................. 18 4.4 Host interface, 8/16 mode (requires external logic device) .......................................................... 19 4.4.1 Instruction write, 8/16 mode................................................................................................. 19 4.4.2 Data write, 8/16 mode........................................................................................................... 19 4.4.3 Data read, 8/16 mode............................................................................................................ 20 4.4.4 Status read, 8/16 mode.......................................................................................................... 20 4.5 Host interface, 16/16 mode (requires external logic device) ........................................................ 21 4.5.1 Instruction write, 16/16 mode............................................................................................... 21 4.5.2 Data write, 16/16 mode......................................................................................................... 21 4.5.3 Data read, 16/16 mode.......................................................................................................... 22 4.5.4 Status read, 16/16 mode........................................................................................................ 22 4.6 External memory timing............................................................................................................... 23 4.6.1 External memory read........................................................................................................... 23 4.6.2 External memory write ......................................................................................................... 23 4.7 Peripheral device timing ............................................................................................................... 24 4.7.1 Peripheral device read........................................................................................................... 24 4.7.2 Peripheral device write ......................................................................................................... 24 5 Pinouts and Pin Descriptions.................................................................................................................. 25 5.1 Pinouts for MC3510 ..................................................................................................................... 25 5.2 CP chip pin description table........................................................................................................ 26 6 Parallel Communication ......................................................................................................................... 29 6.1 Host interface pin description table .............................................................................................. 29 6.2 16-bit Host Interface (IOPIL16) ................................................................................................... 31 MC3510 Technical Specifications vii
6.3
8-bit Host Interface (IOPIL8) ....................................................................................................... 45
7 Application Notes..................................................................................................................................... 60 7.1 Design Tips................................................................................................................................... 60 7.2 RS-232 Serial Interface ................................................................................................................ 62 7.3 RS 422/485 Serial Interface.......................................................................................................... 64 7.4 RAM Interface.............................................................................................................................. 66 7.5 User-defined I/O ........................................................................................................................... 68 7.6 12-bit A/D Interface...................................................................................................................... 70 7.7 16-bit A/D Input ........................................................................................................................... 72 7.8 External Gating Logic Index ........................................................................................................ 74
MC3510 Technical Specifications viii
1 The Pilot Family
MC3110
Number of axes Motor type supported Output format Incremental encoder input Parallel word device input Parallel communication Serial communication S-curve profiling On-the-fly changes Directional limit switches Programmable bit output Software-invertable signals PID servo control Feedforward (accel & vel) Derivative sampling time Data trace/diagnostics PWM output Pulse & direction output Index & Home signals Motion error detection Axis settled indicator DAC-compatible output Position capture Analog input User-defined I/O External RAM support Multi-chip synchronization Chip part numbers Developer's Kit p/n's:
1
MC3310
1 Brushless servo Commutated (6step or sinusoidal)
MC3410
1 Stepping Microstepping
MC3510
1 Stepping Pulse and Direction
1 Brushed servo Brushed servo (single phase)
1 (MC3113)
MC3110 DK3110
1 (MC3313)
MC3310 DK3310
1 (with encoder) (with encoder) (MC3413)
MC3410 DK3410
1 (with encoder) (with encoder) MC3510 DK3510
Parallel communication is available via an additional logic device
Introduction
This manual describes the operational characteristics of the MC3510 Motion Processor from PMD. This device is a member of the MC3000 family of single-chip, single-axis motion processors.
MC3510 Technical Specifications 9
Each device of the MC3000 family is a complete chip-based motion processor providing trajectory generation and related motion control functions for one axis including pulse and direction output or servo loop closure or on-board commutation where appropriate. This family of products provides a software-compatible selection of dedicated motion processors that can handle a large variety of system configurations. The chip architecture not only makes it ideal for the task of motion control, it allows for similarities in software commands, so software written for one motor type can be re-used if the motor type is changed.
Pilot Family Summary
MC3110 - This single-chip, single-axis motion processor outputs motor commands in either Sign/Magnitude PWM or DAC-compatible format for use with brushed servo motors, or with brushless servo motors having external commutation. MC3310 - This single-chip, single-axis motion processor outputs sinusoidally commutated motor signals appropriate for driving brushless motors. Depending on the motor type, the output is a twophase or three-phase signal in either PWM or DAC-compatible format. MC3410 - This single-chip, single-axis motion processor outputs microstepping signals for stepping motors. Two phased signals per axis are generated in either PWM or DAC-compatible format. MC3510 - This single-chip, single-axis motion processor outputs pulse and direction signals for stepping motor systems.
MC3510 Technical Specifications 10
2 Functional Characteristics
2.1 Configurations, parameters, and performance
Configuration Operating modes Single axis, single chip. Open loop (pulse generator is driven by trajectory generator output) Stall detection (pulse generator is driven by trajectory generator output and encoder feedback is used for stall detection) 8/16 parallel (8 bit external parallel bus with 16 bit internal command word size) 16/16 parallel (16 bit external parallel bus with 16 bit internal command word size) Point to point asynchronous serial Multi-drop asynchronous serial 1,200 baud to 416,667 baud -2,147,483,648 to +2,147,483,647 counts -32,768 to +32,767 counts/sample with a resolution of 1/65,536 counts/sample -32,768 to +32,767 counts/sample2 with a resolution of 1/65,536 counts/sample2 0 to 1/2 counts/sample3, with a resolution of 1/4,294,967,296 counts/sample3 S-curve point-to-point (Velocity, acceleration, jerk, and position parameters) Trapezoidal point-to-point (Velocity, acceleration, deceleration, and position parameters) Velocity-contouring (Velocity, acceleration, and deceleration parameters) Motion error window (allows axis to be stopped upon exceeding programmable window) Tracking window (allows flag to be set if axis exceeds a programmable position window) Axis settled (allows flag to be set if axis exceeds a programmable position window for a programmable amount of time after trajectory motion is compete) 50,000 pulses/sec Incremental (up to 5 million counts/sec) Parallel-word (up to 160 million counts/sec) 16 bits 20 kHz (reads all axes every 50 sec) 102.4 sec to 32.767 milliseconds 102.4 sec 2 per axis: one for each direction of travel 2 per axis: index and home signals 1xAxisIn, 1xAxisOut, 1xAtRest Index, Home, AxisIn, AxisOut, PositiveLimit, NegativeLimit (all individually programmable) 8 10-bit analog inputs 256 16-bit wide user defined I/O 65,536 blocks of 32,768 16-bit words per block. Total accessible memory is 2,147,483,648 16 bit words MC3510 Technical Specifications 11
Communication modes
Serial port baud rate range Position range Velocity range Acceleration/ deceleration ranges Jerk range Profile modes
Position error tracking
Maximum pulse rate Maximum encoder rate Parallel encoder word size Parallel encoder read rate Cycle loop timing range Minimum cycle loop time Limit switches Position-capture triggers Other digital signals Software-invertable signals Analog input User defined discrete I/O RAM/external memory support
Trace modes Max. number of trace variables Number of traceable variables Number of host instructions
one-time continuous 4 20 112
MC3510 Technical Specifications 12
2.2
Physical characteristics and mounting dimensions
All dimensions are in inches (with millimeters in brackets).
Dimension
D D1 D2 D3
Minimum (inches)
1.070 0.934 1.088
Maximum (inches)
1.090 0.966 1.112 0.800 nominal
MC3510 Technical Specifications 13
2.3
Environmental and electrical ratings
Storage Temperature (Ts) Operating Temperature (Ta) Power Dissipation (Pd) Nominal Clock Frequency (Fclk) Supply Voltage limits (Vcc) Supply Voltage operating range (Vcc) -55 C to 150 C 0 C to 70 C* 400 mW 20.0 MHz -0.3V to +7.0V 4.75V to 5.25V
* An industrial version with an operating range of -40C to 85C is also available. Please contact PMD for more information.
2.4
System configuration
The following figure shows the principal control and data paths in an MC3510 system.
Host
HostIntrpt
HostData0-15
~HostWrite
~HostRead
~HostSlct
Serial Port
HostCmd
Parallel port
HostRdy
Pilot Motion Processor
System clock (40 MHz)
Home
Index
B
A
Negative
16 bit data/address bus
External memory
Limit switches
Motor Amplifier
User I/O
Parallel-word input
Serial port configuration
The shaded area shows the CPLD/FPGA that must be provided by the designer if parallel communication is required. A description and the necessary logic (in the form of schematics) of this device are detailed in section 6 of this manual. The CP chip contains the profile generator, which calculates velocity, acceleration, and position values for a trajectory. The output of the trajectory generator is used to produce pulse and direction signals that control motor position.
MC3510 Technical Specifications 14
Direction
AxisOut
Positive
AtRest
AxisIn
Pulse
Encoder
Parallel Communication PLD/FPGA
20MHz clock
CP
Optional axis position information returns to the motion in the form of incremental encoder feedback or in the form of parallel-word feedback. This position feedback may be used to detect motor stalling errors.
2.5
Peripheral device address mapping
Device addresses on the CP chip's data bus are memory-mapped to the following locations: Address 0200h 0800h 1000h 2000h 4000h 8000h Device Serial port data Parallel-word encoder User-defined RAM page pointer Motor-output DACs Parallel interface Description Contains the configuration data (transmission rate, parity, stop bits, etc) for the asynchronous serial port Base address for parallel-word feedback devices Base address for user-defined I/O devices Page pointer to external memory Base address for motor-output D/A converters Base address for parallel interface communication
MC3510 Technical Specifications 15
3 Electrical Characteristics
3.1 DC characteristics
(Vcc and Ta per operating ratings, Fclk = 20.0 MHz)
Symbol Vcc Idd Vih Vil Vihclk Voclk Vihreset Voh Vol Iout Iin Cio Zai Ednl Einl Parameter Supply Voltage Supply Current Minimum 4.75 V Maximum 5.25 V 80 mA Vcc + 0.3 V 0.8 V Vcc + 0.3 V 0.7 V Vcc + 0.3 V @CP Io = -23 mA @CP Io = 6 mA @CP 0 < Vout < Vcc @CP 0 < Vi < Vcc @CP typical Conditions open outputs
Input Voltages Logic 1 input voltage 2.0 V Logic 0 input voltage -0.3 V Logic 1 voltage for clock pin 3.0 V (ClockIn) Logic 0 voltage for clock pin -0.3 V (ClockIn) Logic 1 voltage for reset pin (reset) 2.2 V Logic 1 Output Voltage Logic 0 Output Voltage Output Voltages 2.4 V
0.33 V Other -5 A -10 A 15 pF 9k 1.5 LSB +/-1.5 LSB 5 A 10 A
Tri-State output leakage current Input current Input/Output capacitance
Analog Input Analog input source impedance Differential nonlinearity error. -1 Difference between the step width and the ideal value. Integral nonlinearity error. Maximum deviation from the best straight line through the ADC transfer characteristics, excluding the quantization error.
3.2
AC characteristics
See timing diagrams, Section 4, for Tn numbers. The symbol "~" indicates active low signal.
Timing Interval Clock Frequency (Fclk) Clock Pulse Width Clock Period (note 2) Encoder Pulse Width Dwell Time Per State ~HostSlct Hold Time Tn T1 T2 T3 T4 T6 Minimum > 0 MHz 25 nsec 50 nsec 150 nsec 75 nsec 0 nsec Maximum 20 MHz (note 1)
MC3510 Technical Specifications 16
Timing Interval ~HostSlct Setup Time HostCmd Setup Time HostCmd Hold Time Read Data Access Time Read Data Hold Time ~HostRead High to HI-Z Time HostRdy Delay Time ~HostWrite Pulse Width Write Data Delay Time Write Data Hold Time Read Recovery Time (note 2) Write Recovery Time (note 2) Read Pulse Width Address Setup Delay Time Data Access Time Data Hold Time Address Setup Delay Time Address Setup to WriteEnable High RAMSlct Low to WriteEnable High Address Hold Time WriteEnable Pulse Width Data Setup Time Data Setup before Write High Time Address Setup Delay Time Data Access Time Data Hold Time Address Setup Delay Time Address Setup to WriteEnable High PeriphSlct Low to WriteEnable High Address Hold Time WriteEnable Pulse Width Data Setup Time Data Setup before Write High Time Read to Write Delay Time Reset Low Pulse Width RAMSlct Low to Strobe Low Strobe High to RAMSlct High WriteEnable Low to Strobe Low Strobe High to WriteEnable High PeriphSlct Low to Strobe Low Strobe High to PeriphSlct High
Tn T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T50 T51 T52 T53 T54 T55 T56
Minimum 0 nsec 0 nsec 0 nsec
Maximum
100 nsec 70 nsec 0 nsec 60 nsec 60 nsec 70 nsec
25 nsec 10 nsec 20 nsec 150 nsec 35 nsec
7 nsec 19 nsec 2 nsec 7 nsec 72 nsec 79 nsec 17 nsec 39 nsec 3 nsec 42 nsec 7 nsec 71 nsec 2 nsec 7 nsec 122 nsec 129 nsec 17 nsec 89 nsec 3 nsec 92 nsec 50 nsec 5.0 sec 1 nsec 4 nsec 1 nsec 3 nsec 1 nsec 4 nsec
Note 1 Performance figures and timing information valid at Fclk = 20.0 MHz only. For timing information and performance parameters at Fclk < 20.0 MHz, refer to section 7.1. Note 2 The clock low/high split has an allowable range of 45-55%.
MC3510 Technical Specifications 17
4 I/O Timing Diagrams
For the values of Tn, please refer to the table in Section 3.2. The host interface timing shown in diagrams 4.4 and 4.5 is only valid when an external logic device is used to provide a parallel communication interface. Refer to section 6 for more information.
4.1
Clock
ClockIn
T1 T1 T2
4.2
Quadrature encoder input
T3 T3
Quad A
T4 T4
Quad B
~Index
4.3
Reset
Vcc ClockIn
~RESET
T50
MC3510 Technical Specifications 18
4.4
4.4.1
Host interface, 8/16 mode (requires external logic device)
Instruction write, 8/16 mode
T7 T6
see note
~HostSlct
T8 T9
HostCmd
T14 T18
see note
T14
~HostWrite
T16 T16 Low byte
HostData0-7
High byte
HostRdy
T15 T15 T13 Note: If setup and hold times are met, ~HostSlct and HostCmd may be de-asserted at this point.
4.4.2
Data write, 8/16 mode
~HostSlct
T7 see note T6
HostCmd
T8 see note
T9
T14
T18
T14
~HostWrite
T16
T16 Low byte
HostData0-7
High byte
HostRdy
T15 T15 T13 Note: If setup and hold times are met, ~HostSlct and HostCmd may be de-asserted at this point.
MC3510 Technical Specifications 19
4.4.3
Data read, 8/16 mode
T7 T6 see note
~HostSlct
HostCmd
T8
T9 see note
~HostRead
T19 T12 High-Z High byte T10 T11 High-Z High-Z
HostData0-7
Low byte
HostRdy
T13 Note: If setup and hold times are met, ~HostSlct and HostCmd may be de-asserted at this point.
4.4.4
Status read, 8/16 mode
~HostSlct
T7 T6
HostCmd ~HostRead
T8 T17 T19
T9
T12
HostData0-7
High-Z
High byte T10 T11
High-Z
Low byte
High-Z
MC3510 Technical Specifications 20
4.5
4.5.1
Host interface, 16/16 mode (requires external logic device)
Instruction write, 16/16 mode
~HostSlct
T7 T6
HostCmd
T8 T14 T9
~HostWrite
T16
HostData0-15
HostRdy
T15 T13
4.5.2
Data write, 16/16 mode
T7 T6
~HostSlct
T9
T8
HostCmd
T14
~HostWrite
T16
HostData0-15
HostRdy
T15 T13
MC3510 Technical Specifications 21
4.5.3
Data read, 16/16 mode
~HostSlct
T7 T6
HostCmd
T8
T9
~HostRead
T19
T12
HostData0-15
High-Z
High-Z
T10
T11
HostRdy
T13
4.5.4
Status read, 16/16 mode
T7 T6
~HostSlct
HostCmd
T8 T19 T9
~HostRead
T12
HostData0-15
High-Z
High-Z
T10
T11
MC3510 Technical Specifications 22
4.6
4.6.1
External memory timing
External memory read
Note: PMD recommends using memory with an access time no greater than 15 nsec.
T20 T40
~RAMSlct
Addr0-Addr15
W/~R
~WriteEnbl Data0-Data15
T51
T21
T52
~Strobe
4.6.2
External memory write
~RAMSlct
T23 T24
Addr0-Addr15
T25 T26
R/~W
W/~R
T29
~WriteEnbl
T28 T27 T27
Data0-Data15
T53 T54
~Strobe
MC3510 Technical Specifications 23
4.7
4.7.1
Peripheral device timing
Peripheral device read
T30 T40
~PeriphSlct
Addr0-Addr15
W/~R
T31
~WriteEnbl Data0-Data15
T55
T31
T32
T56
~Strobe
4.7.2
Peripheral device write
~PeriphSlct
T33 T34
Addr0-Addr15
T35 T36
R/~W
W/~R
T39
~WriteEnbl
T38 T37 T37
Data0-Data15
T53 T54
~Strobe
MC3510 Technical Specifications 24
5 Pinouts and Pin Descriptions
5.1 Pinouts for MC3510
2, 7, 13, 21, 35, 36, 40, 47, 50, 52, 60, 62, 66, 93, 103, 121
1 4 6 130 129 41 132 43 44 99 98 58 110 111 112 114 115 116 117 118 119 122 123 124 125 126 127 128 9 10 11 12 15 16 17 18 19 22 23 24 25 26 27 28
~WriteEnbl R/~W ~Strobe ~PeriphSlct ~RAMSlct ~Reset W/~R SrlRcv SrlXmt SrlEnable ~HostIntrpt ClockIn Addr0 Addr1 Addr2 Addr3 Addr4 Addr5 Addr6 Addr7 Addr8 Addr9 Addr10 Addr11 Addr12 Addr13 Addr14 Addr15 Data0 Data1 Data2 Data3 Data4 Data5 Data6 Data7 Data8 Data9 Data10 Data11 Data12 Data13 Data14 Data15
VCC
CP
AnalogVcc AnalogRefHigh AnalogRefLow AnalogGnd Analog1 Analog2 Analog3 Analog4 Analog5 Analog6 Analog7 Analog8 PosLim1 NegLim1 AxisOut1 AxisIn1 Direction1 Pulse1 AtRest1 QuadA1 QuadB1 ~Index1 ~Home1
84 85 86 87 74 89 75 88 76 83 77 82 63 64 94 72 105 106 107 67 68 69 70
I/OIntrpt PrlEnable
53 65
GND 3, 8, 14, 20, 29, 37, 46, 56, 59, 61, 71, 92, 104, 113, 120
Unassigned 5, 30-34, 38, 39, 42, 45, 48, 49, 51, 54, 55, 57, 73, 90, 91, 9597, 100-102, 108, 109, 131
AGND 78-81
MC3510 Technical Specifications 25
5.2
CP chip pin description table
Pin Name and number Direction
~WriteEnbl R/~W ~Strobe ~PeriphSlct ~RAMSlct ~Reset W/~R SrlRcv SrlXmt SrlEnable ~HostIntrpt I/OIntrpt 1 4 6 130 129 41 132 43 44 99 98 53
Description
When low, this signal enables data to be written to the bus. This signal is high when the CP chip is performing a read, and low when it is performing a write. This signal is low when the data and address are valid during CP communications. This signal is low when peripheral devices on the data bus are being addressed. This signal is low when external memory is being accessed. This is the master reset signal. When brought low, this pin resets the processor to its initial conditions. This signal is the inverse of R/~W; it is high when R/~W is low, and vice versa. For some decode circuits, this is more convenient than R/~W. This pin receives serial data from the asynchronous serial port. If serial communication is not used, this pin should be tied to Vcc. This pin transmits serial data to the asynchronous serial port. This pin sets the serial port enable line. SrlEnable is always high for the point-topoint protocol and is high during transmission for the multi-drop protocol. When low, this signal causes an interrupt to be sent to the host processor. This signal interrupts the CP chip when a host I/O transfer is complete. It should be connected to CPIntrpt of the parallel interface chip. If the parallel interface is disabled (see below) this signal can be left unconnected or tied to Vcc. This signal enables/disables the parallel communication with the host. If this signal is tied high, the parallel interface is enabled. If this signal is tied low the parallel interface is disabled. See section 6 of this manual for more information on parallel communication.
output output output output output input output input output output output input
PrlEnable
65
input
WARNING! This signal should only be tied high if an external logic device that implements the parallel communication logic included in the design. This signal is an output during device reset and as such any connection to GND or Vcc must be via a series resistor.
Data0 Data1 Data2 Data3 Data4 Data5 Data6 Data7 Data8 Data9 Data10 Data11 Data12 Data13 Data14 Data15 9 10 11 12 15 16 17 18 19 22 23 24 25 26 27 28
bi-directional
Multi-purpose data lines. These pins comprise the CP chip's external data bus, used for all communications with peripheral devices such as external memory or DACs. They may also be used for parallel-word input and for user-defined I/O operations.
MC3510 Technical Specifications 26
Pin Name and number Direction
Addr0 Addr1 Addr2 Addr3 Addr4 Addr5 Addr6 Addr7 Addr8 Addr9 Addr10 Addr11 Addr12 Addr13 Addr14 Addr15 ClockIn AnalogVcc 110 111 112 114 115 116 117 118 119 122 123 124 125 126 127 128 58 84
Description
Multi-purpose Address lines. These pins comprise the CP chip's external address bus, used to select devices for communication over the data bus. They may be used for DAC output, parallel word input, or user-defined I/O operations. See the Pilot Motion Processor User's Guide for a complete memory map.
output
input input
AnalogRefHigh 85
input
AnalogRefLow
86
input
AnalogGND
87
Analog1 Analog2 Analog3 Analog4 Analog5 Analog6 Analog7 Analog8 Pulse1
74 89 75 88 76 83 77 82 106
input
This is the clock signal for the Motion Processor. It is driven at a nominal 20MHz. CP chip analog power supply voltage. This pin must be connected to the analog input supply voltage, which must be in the range 4.5-5.5 V If the analog input circuitry is not used, this pin must be connected to Vcc. CP chip analog high voltage reference for A/D input. The allowed range is AnalogRefLow to AnalogVcc. If the analog input circuitry is not used, this pin must be connected to Vcc. CP chip analog low voltage reference for A/D input. The allowed range is AnalogGND to AnalogRefHigh. If the analog input circuitry is not used, this pin must be connected to GND. CP chip analog input ground. This pin must be connected to the analog input power supply return. If the analog input circuitry is not used, this pin must be connected to GND. These signals provide general-purpose analog voltage levels, which are sampled by an internal A/D converter. The A/D resolution is 10 bits. The allowed range is AnalogRefLow to AnalogRefHigh. Any unused pins should be tied to AnalogGND. If the analog input circuitry is not used, these pins should be tied to GND.
output
Direction1
105
output output input
AtRest1
107
QuadA1 QuadB1
67 68
This pins provides the pulse (also called step) signal to the motor amplifier. A "step" occurs when the signal transitions from a high state to a low state. This default operation can be changed using the SetSignalSense command. Refer to the Pilot Programmer's Reference for more information. This pin indicates the direction of motion and works in conjunction with the pulse signal. A high level on this signal indicates a positive direction move and a low level indicates a negative direction move. The AtRest signal indicates that the axis is at rest and the step motor can be switched to low power or standby. A high level on this signal indicates the axis is at rest. A low signal indicates the axis is in motion. These pins provide the A and B quadrature signals for the incremental encoder. When the axis is moving in the positive (forward) direction, signal A leads signal B by 90. The theoretical maximum encoder pulse rate is 5.1 MHz. Actual maximum rate will vary, depending on signal noise. NOTE: Many encoders require a pull-up resistor on each signal to establish a proper high signal. Check your encoder's electrical specification. MC3510 Technical Specifications 27
Pin Name and number Direction
~Index1 69
Description
This pin provides the Index signal for the incremental encoder. A valid index pulse is recognized by the chip when this signal transitions from high to low.
input
There is no internal gating of the index signal with the encoder A and B inputs. This must be performed externally if desired. Refer to the Application Notes section at the end of this manual for an example.
~Home1 70
input
This pin provides the Home signal, general-purpose inputs to the positioncapture mechanism. A valid Home signal is recognized by the chip when ~Home goes low.
WARNING! If this pin is not used, its signal should be tied high.
PosLim1 63
input
This signal provides input from the positive-side (forward) travel limit switch. On power-up or Reset this signal defaults to active low interpretation, but the interpretation can be set explicitly using the SetSignalSense instruction.
WARNING! If this pin is not used, its signal should be tied high.
NegLim1 64
input
This signal provides input from the negative-side (reverse) travel limit switch. On power-up or Reset this signal defaults to active low interpretation, but the interpretation can be set explicitly using the SetSignalSense instruction.
WARNING! If this pin is not used, its signal should be tied high. This signal is an output during device reset and as such any connection to GND or Vcc must be via a series resistor.
AxisOut1 AxisIn1 94
Vcc
This pin can be programmed to track the state of any bit in the status registers. If this pin is not used it may be left unconnected. 72 input This is a general-purpose or programmable input. It can be used as a breakpoint input, to stop a motion axis, or to cause an Update to occur. If this pin is not used it may be left unconnected. 2, 7, 13, 21, 35, 36, 40, CP digital supply voltage. All of these pins must be connected to the supply 47, 50, 52, 60, 62, 66, voltage. Vcc must be in the range 4.75 - 5.25 V 93, 103, 121
output
WARNING! Pin 35 must be tied HIGH with a pull-up resistor. A nominal value of 22K Ohms is suggested.
GND
AGND unassigned unassigned
3, 8, 14, 20, 29, 37, 46, CP ground. All of these pins must be connected to the power supply return. 56, 59, 61, 71, 92, 104, 113, 120 78-81 These signals must be tied to AnalogGND. If the analog input circuitry is not used, these pins must be tied to GND. 45, 48, 49, 51, 54, 55, These signals may be connected to GND for better noise immunity and reduced 73, 90, 91, 108, 109 power consumption or they can be left unconnected (floating). 5, 30-34, 38, 39, 42, These signals must be left unconnected (floating). 57, 95, 96, 97, 100, 101, 102, 131
MC3510 Technical Specifications 28
6 Parallel Communication
With the addition of an external logic device, the Pilot motion processor can communicate with a host processor using a parallel data stream. This offers a higher communication rate than a serial interface and may be used in configurations where a serial connection is not available or not convenient. This section details the required logic that must be implemented in the external device as well as the necessary connections to the CP chip. The reference design files for the parallel interface chip, in Actel/ViewLogic format, are available from PMD. There are two versions of the design, one for interfacing with host processors that have an 8-bit data bus and one for host processors that have a 16-bit data bus. The designs are called IOPIL8 and IOPIL16 respectively. The interface to the CP chip is essentially identical in both. The function of the I/O chip is to provide a shared-memory style interface between the host and CP chip, comprised of four 16-bit wide locations. These are used for transferring commands and data between the host and Pilot motion processor. The CP chip accesses the command/data registers using its 16-bit external data bus while the host accesses the registers via a parallel interface with chip select, read, write and command/data signals. If necessary, the host side interface can be modified by the designer to match specific requirements of the host processor.
6.1
Host interface pin description table
Pin Name
HostCmd
Direction
input output
Description
This signal is asserted high to write a host instruction to the motion processor, or to read the status of the HostRdy and HostIntrpt signals. It is asserted low to read or write a data word. This signal is used to synchronize communication between the motion processor and the host. HostRdy will go low (indicating host port busy) at the end of a read or write operation according to the interface mode in use, as follows: Interface Mode HostRdy goes low 8/16 after the second byte of the instruction word after the second byte of each data word is transferred 16/16 after the 16-bit instruction word after each 16-bit data word serial n/a HostRdy will go high, indicating that the host port is ready to transmit, when the last transmission has been processed. All host port communications must be made with HostRdy high (ready). A typical busy-to-ready cycle is 12.5 microseconds, but can be substantially longer, up to 100 microseconds. When ~HostRead is low, a data word is read from the motion processor. When ~HostWrite is low, a data word is written to the motion processor. When ~HostSlct is low, the host port is selected for reading or writing operations. I/O chip to CP chip interrupt. This signal sends an interrupt to the CP chip whenever a host-chipset transmission occurs. It should be connected to CP chip pin 53, I/OIntrpt. This signal is high when the I/O chip is reading data from the I/O chip, and low when it is writing data. It should be connected to CP chip pin 4, R/W. This signal goes low when the data and address become valid during Motion processor communication with peripheral devices on the data bus, such as external memory or a DAC. It should be connected to CP chip pin 6, Strobe. MC3510 Technical Specifications 29
HostRdy
~HostRead ~HostWrite ~HostSlct CPIntrpt
input input input output input input
CPR/~W CPStrobe
Pin Name
CPPeriphSlct CPAddr0 CPAddr1 CPAddr15 MasterClkIn CPClk
Direction
input input input output bi-directional, tri-state
Description
This signal goes low when a peripheral device on the data bus is being addressed. It should be connected to CP chip pin 130, PeriphSlct. These signals are high when the CP chip is communicating with the I/O chip (as distinguished from any other device on the data bus). They should be connected to CP chip pins 110 (Addr0), 111 (Addr1), and 128 (Addr15). This is the master clock signal for the motion processor. It is driven at a nominal 40 MHz This signal provides the clock pulse for the CP chip. Its frequency is half that of MasterClkIn (pin 89), or 20 MHz nominal. It is connected directly to the CP chip I/Oclk signal (pin 58). These signals transmit data between the host and the Motion processor through the parallel port. Transmission is mediated by the control signals ~HostSlct,
~HostWrite, ~HostRead and HostCmd.
HostData0 HostData1 HostData2 HostData3 HostData4 HostData5 HostData6 HostData7 HostData8 HostData9 HostData10 HostData11 HostData12 HostData13 HostData14 HostData15 CPData0 CPData1 CPData2 CPData3 CPData4 CPData5 CPData6 CPData7 CPData8 CPData9 CPData10 CPData11 CPData12 CPData13 CPData14 CPData15
In 16-bit mode, all 16 bits are used (HostData0-15). In 8-bit mode, only the loworder 8 bits of data are used (HostData0-7).
bi-directional
These signals transmit data between the I/O chip and pins Data0-15 of the CP chip, via the motion processor data bus.
MC3510 Technical Specifications 30
6.2
16-bit Host Interface (IOPIL16)
This design implements a parallel interface with a host processor utilizing a 16-bit data bus. An understanding of the underlying operation of the design is only necessary if the designer intends to make modifications. In most cases this design can be implemented without changes. The following notes should be read while referencing the schematics. IOPIL16 1 is the top level schematic. The timing for the host to I/O chip communication can be found in section 4.5 and the timing for the CP to I/O chip communication can be found in section 4.7. The description below identifies the key elements of each schematic starting with the host side signals. The paragraph title identifies the key schematic(s) being described in the text. IOPIL16 3 The host interface is shown in sheet IOPIL16 3. The incoming data HD[15:0] is latched in the transparent latches when ~HG1 and ~HG2 go high. This would be the result of a write from the host to the CP. The latched data HI[15:8] and HI[7:0] go to schematic IOPIL16 1 and IOPIL16 5. Data from the interface to the host, HO[15:8] and HO[7:0] is enabled onto the host bus, HD[15:0], by HOES2 and HOES1 respectively. The output latches, which present the data during a host read, are always transparent because GOUT is connected to VDD. The latched I/O is an I/O option on the Actel part used and could be omitted in the host interface if a different CPLD or FPGA does not have this feature. IOPIL16 1 The control for the host interface starts on IOPIL16 1. HOES1 and HOES2 are the AND of ~HSEL and ~HRD and enable read data onto the host bus, as previously described. HRDY is a handshaking signal to the host to allow asynchronous communication between the host and the CP. The host must wait until HRDY is true before attempting to communicate with the CP. This signal is copied as a bit in the host status register. The host status register may be read at any time to determine the state of HRDY, or the HRDY output may be used as an interrupt to the host. ~HSEL, ~HRD, ~HWR, and HA0 are the buffered inputs of the host control signals. HOST INTERFACE/IOPIL16 5 Data from the host HI[15:8] and HI[7:0] is written into REG1 and REG2 on the schematic HOST INTERFACE by ~EN1 and ~EN2. These registers have a 2 to 1 multiplexed input with both the host data and the CP data being written to these registers. This is convenient for diagnostic purposes and is very efficient in the Actel A42MX FPGA's, which are multiplexer based but if the configuration of the logic device used demands it, separate registers could be used for the host and CP data. The schematic for this register is shown as DFME8. Only commands and checksums are written to registers REG1 and REG2 while data is written and read from the set of data registers, DATREG shown on IOPIL16 5. These 3 data registers buffer data sent to and from the CP, reducing the number of interrupts the CP must handle. The output from REG1 and REG2, CIQ[15:8] and CIQ[7:0] go to IOPIL16 5, where they are multiplexed with the other data registers. The multiplexed result, IQ[15:8] and IQ[7:0], is multiplexed with HST[15:8] and HST[7:0] - the output of the host status registers REG3 and REG4. As previously mentioned, HRDY becomes HST15 so it can be read by the host. The rest of the status register is written by the CP to provide information to the host. HA0 acts as an address bit, and usually is an address bit on the bus. When the host is writing, HA0 low indicates data and HA0 high indicates a command. When the host is reading, HAO low indicates data and HA0 high indicates status. Read status is the only transaction
MC3510 Technical Specifications 31
allowed while HRDY is low. During a host write the AND gate (G1:HOST INTERFACE) and two flops latch the incoming data in the interface latches by driving ~HG1, and ~HG2 low from the start of the write transaction until the first negative clock transition after the first positive transition following the start of the write cycle. This tail-biting circuit removes the requirement for hold time on the data bus. HICTLA Most of the control logic for the host interface is shown on schematic HICTLA. The sequencer at the top generates HCYC one clock interval after the interface has been accessed and the host has finished the transaction. The nature of the transaction, rd/wr, command/data, and read status is preserved in the three flops F13, F8, and F9. A host write or a CP write, DSIW, enable REG1 and REG2 on the HOST INTERFACE schematic discussed previously. A host data write generates ~ENHD1 and ~ENHD2 for the data registers on the DATREG schematic. The logic at the bottom of the page generates the CP interrupt, the HRDY and the HCMDFL. The HCMDFL is used in the CP status to indicate a command. DSIW, the CP writing to REG1 and REG2 on the HOST INTERFACE schematic clears the interrupt and reasserts HRDY. HRDY is de-asserted during all host transactions except read status, and stays de-asserted until the CP has completed the DSIW cycle that clears the interrupt and reasserts HRDY. As mentioned previously data transfers to and from the host use the data registers and do not interrupt the CP. The CP knows the number of data transfers that must take place after decoding the command. It places this number, 0-3, in the 2 least significant bits of the host status register, HST[1:0]. These become DPNT[1:0] on this page of the schematic and enable an interrupt at 0 for a read and 1 or 0 for a write. The CP always leaves theses bit set to 0 unless setting up a multiple word data transfer. If INTEN is true and LRDST, latched read status, is false, HCYC will generate an interrupt to the CP. This will also hold HRDY false until after the CP writes to the interface register, DSIW, thereby generating ~CLRFLGS. IOPIL16 4 The CP interface is shown in sheet IOPIL16 4. The incoming data DSD[15:0] is latched in the transparent latches when ~DG1 and ~DG2 go high. This occurs at the completion of a write from the CP to the I/O chip. The latched data DSI[15:8] and DSI[7:0] go to schematic IOPIL16 1 and IOPIL16 5. DSI[7:0] also goes to IOPIL16 2. Data from the interface to the CP, DO[15:8] and DO[7:0] is enabled onto the CP bus, DSD[15:0], by DOE2 and DOE1 respectively. The output latches, which present the data during a CP read, are always transparent because GOUT is connected to VDD. The latched I/O in the Actel part contains both input and output latches. The output latches could be omitted in the CP interface if a different CPLD or FPGA does not have this feature. The two incoming CP address bits CPA0 and CPA1 are also latched using ~DG3. The 20CK signal is the clock for the CP. This is a 20 MHz clock derived from a 40 MHz clock input. IOPIL16 2 The CP control starts on IOPIL16 2. The I/O control is generated from ~CPSTRB, ~CPIS, CPSEL and R/W. ~DG1, ~DG2, and ~DG3 latch the incoming data and DOE1 and DOE2 outenable the data from this chip to the CP. F2 and F4 tail-bite the write to avoid having to specify hold times on the data. Flop F1 divides the 40MHz clock down to 20 MHz. A 20 MHz clock could be used for this interface and the CP.
MC3510 Technical Specifications 32
DSPWA The CP write control is contained on schematic DSPWA. The CP interface uses page addressing to save I/O pins. F0, F1 and F2 make up the page register. In addition there are the 2 address bits, LA0 and LA1. A write to address 0 selects the page register with DSI[2:0] going to the page register and selecting the page for the successive transfers. A read from address 0 reads the status register on all pages. Pages 4 and 6 are the only ones implemented in this device. L1 latches the r/w level. The write decoding generates DSIW which enables writes to the DFME8 registers reg1 and reg2 shown on the HOST INTERFACE schematic. DSIW also clears the CP interrupt and restores HRDY. DSWST writes to the host status register also shown on the HOST INTERFACE schematic. DSWDREG implements writing to the data registers shown on IOPIL16 5 and DATREG. Finally the logic at the bottom of the page generates CPCYC, a 1-clock interval after the CP cycle is over that implements the actual writes to the registers. The use of the data bus latches and the post bus cycle transfers keeps as much of the logic synchronous as possible given two asynchronous devices, without requiring clocking at several times the bus speed. DSPRA The CP read control is contained on schematic DSPRA. The 2 by 16 bit mux selects CP status if the CP latched address is 0 and IQ[15:0] if the address is not 0. The only significant status bits are bits 15 (indicating the CP is interrupting the host), bits 13 and 14 (both 0 indicating a 16 bit host interface) and bit 0 (set to 1 during a host command transfer and 0 during data transfer). HOST INTERFACE Both the CP and the host use a special mode to transfer data to avoid unnecessary CP interrupts. This special mode is under the control of the CP and is transparent to the host. When the CP receives a command from the host it initializes the transfer by setting the number of transfers expected (0,1,2 or 3) in the 2 LSB's of the host status register, REG3 and REG4 on HOST INTERFACE. This write (DSWST) also loads these bits into the 2 bit down counter DCNT2 on IOPIL16 5. Note that a Q8 low, which indicates a host command, asynchronously clears this register enabling interrupts on schematic HICTLA. If DPNT[1:0] is not 0 and Q8 is high, indicating a host data transfer, and SINT goes high indicating the end of a host cycle the counter is decremented. MXAD2 selects address RA from the CP latched address bits if the page register contains 6, or the counter contents DPNT[1:0] if not. This allows the CP to have direct access to registers 1, 2, and 3, using addresses 1,2,and 3 on page 6. The host on the other hand can only read or write to the data register, HA0 low and the counter will auto decrement from 3 down to 0 allowing the host to access the registers on DATREG where REG1=R1 and R2, REG2=R3 and R4, and REG3=R5 and R6. The writes are enabled by the two decoders DECE2X4, while the reads are selected by the two 4x8 muxes, MUX1 and MUX2 controlled by the two 2x1 muxes MDS1 and MDS0. The output data IQ[15:0] goes to HOST INTERFACE schematic below IOPIL16 1 and to DSPRA below IOPIL16 2. The write data is HI[15:8], HI[7:0] from the host and DSI[15:8] and DSI[7:0] from the CP.
MC3510 Technical Specifications 33
A
B
C
D
HINTF HSTSEL
PAD
INBUF
IN17
Y
HSEL
HSEL HRD
HOST INTERFACE (HINTRFA) HO[7:0] HO[7:0] 1 HO[15:8] HO[15:8]
HSTRD 1
PAD
INBUF
IN18
Y
HWR HRD HA0
HSTWR
PAD
INBUF
IN19
Y
HI[7:0] HWR HI[15:8] HI[15:8] HI[7:0]
HADR0
PAD
INBUF
IN20
Y
HA0
DSI[15:8] DSI[15:8] DSI[7:0] DSI[7:0] DPNT[1:0] HST[1:0] Q8 DSWST DSIW DSWST SINT DSIW CIQ[15:8] CIQ[7:0]
CIQ[7:0] CIQ[15:8]
Q8
SINT
2
HG1 HG2 IQ[7:0] IQ[7:0] HST14 IQ[15:8] IQ[15:8] HCMDFL DSPINTR CLK CLK HST15 ENHD1 ENHD2 HRD HSEL
HG1 HG2 ST15 ST0 DSPINTR
OUTBUF
2
RDY ENHD1 ENHD2
D
PAD
HRDY
A B
AND2B
Y
HOES1
3 HRD HSEL
A B
AND2B
3
Y
HOES2
OUTBUF
DSPINTR
D
OUT5
PAD
DSPINT
4
IOPIL16 1
22 OCT 2002
A B C DRAWN BY: D
4
DBS
A
B
C
D
PNT0 PNT1
CSEL0 CSEL1 DSPRA
DSWDREG 1 DSI[7:0] DSI[7:0] DSWST PP6 PP4 DSIW
DSWDREG ST0 ST15 DSIW DSWST PP6 PP4 IQ[15:0] IQ[15:0] ST0 ST15 1
IN27 CS
PAD
INBUF
Y
IN28
CPSEL DG3 DG3
CPR-W
PAD
INBUF
Y
DO[15:0] LA0 IN26 LA0 LA1 2 CPSEL R/W CPSTRB R/W CPSTRB CPIS CLK DSPWA CLKINT CPCYC CPCYC LA0 LA1 LA0 LA1 DSPRA DO[15:0]
2
STRB
PAD
INBUF
Y
IN30
LA1
IS
PAD
INBUF
Y
CKBUF 20CK
CPIS
A
Y
CLK
CPSTRB CPIS CPSEL
A B C
G1
NAND3B
Y CSACC
A B
R/W 3 G2
AND4B
C D A B C D
A B C A B C
Y
F1 DOE1 IB1 CLKIN
INBUF
D PAD Y
40CK
QN
DF1A
20CK 3
CLK
G3
AND4B
Y
DOE2
G4
NAND3B
Y DG1
G5
NAND3B
Y DG2
F2 F4
A G6
4 CSACC CQ3
CSACC
D
DF1
Q
CQ1
D
DF1
Q
CQ3
B C D
NAND4B
Y DG3
CLK
CLK
CLK
4
IOPIL16 2
24 OCT 2002
DRAWN BY: D
DBS
A
B
C
A
B
C
D
HIGH SLEW
HO0
D
E D Q
PAD
HIGH SLEW
HIGH SLEW
HIGH SLEW
HD0 HO4
D
E D Q
PAD
HD4
HO8
D
E D Q
PAD
HD8
HO12
D
E D Q
PAD
HD12
GOUT
1
G
Q HI0
VDD
GOUT
G
Q HI4
VDD
GOUT
G
Q HI8
VDD
GOUT
G
Q HI12
1
VDD GIN
D
BBDLHS
Q
D
BBDLHS
Q
D
BBDLHS
Q
D
BBDLHS
Q
G
GIN
G
GIN
G
GIN
G
HIGH SLEW
HO1
D
E D Q
PAD
HIGH SLEW
HIGH SLEW
HIGH SLEW
HD1 HO5
D
E D Q
PAD
HD5
HO9
D
E D Q
PAD
HD9
HO13
D
E D Q
PAD
HD13
GOUT
G
Q HI1
GOUT Q
G
Q HI5
GOUT
G
Q HI9
GOUT
G
Q HI13
D
BBDLHS
D
BBDLHS
Q
D
BBDLHS
Q
D
BBDLHS
Q
GIN 2 HO2
G
HIGH SLEW
GIN
G
HIGH SLEW
GIN
G
HIGH SLEW
GIN
G
2
HIGH SLEW
D
E D Q
PAD
HD2 HO6
D
E D Q
PAD
HD6
HO10
D
E D Q
PAD
HD10
HO14
D
E D Q
PAD
HD14
GOUT
G
Q HI2
GOUT Q
G
Q HI6
GOUT
G
Q HI10
GOUT
G
Q HI14
D
BBDLHS
D
BBDLHS
Q
D
BBDLHS
Q
D
BBDLHS
Q
GIN
G
GIN
G
HIGH SLEW
GIN
G
GIN
G
HIGH SLEW
HIGH SLEW
HO3
D
E D Q
PAD
HD3
HO7
D
E D Q
PAD
HIGH SLEW
HD7 HO11
D
E D Q
PAD
HO15 HD11
D
E D Q
PAD
HD15
GOUT
3
G
Q HI3
GOUT
G
Q HI7
GOUT Q
GOUT G
Q HI11 GIN
G
Q 3 HI15
D
BBDLHS
Q
D
BBDLHS
D
BBDLHS
Q
D
BBDLHS
Q
GIN
G
GIN
G
HI[7:0]
GIN
G
G
HI[15:0]
HG1 HO[7:0]
HG1 HO[15:8] HG2
HG2 VCC HOES1 Y VDD 4 HOES2
IOPIL16 3
21 OCT 2002
A B C DRAWN BY: D
4
DBS
A DOE1
HIGH SLEW
B
C
D
DOE1 PAD
HIGH SLEW
DOE2
HIGH SLEW
DOE2
HIGH SLEW
DO0
D
E D Q
DSD0 DO4
D
E D Q
PAD
DSD4
DO8
D
E D Q
PAD
DSD8
DO12
D
E D Q
PAD
DSD12
VDD 1
GOUT
G
Q DSI0
VDD
GOUT
G
Q DSI4
VDD
GOUT
G
Q DSI8
VDD
GOUT
G
1 Q DSI12
D
BBDLHS
Q
D
BBDLHS
Q
D
BBDLHS
Q
D
BBDLHS
Q
GIN DOE1
G
DOE1 PAD
GIN
G
DOE2
HIGH SLEW
GIN
G
DOE2
HIGH SLEW
GIN
G
HIGH SLEW
DO1
D
E D Q
HIGH SLEW
DSD1 DO5
D
E D Q
PAD
DSD5
DO9
D
E D Q
PAD
DSD9
DO13
D
E D Q
PAD
DSD13
GOUT
G
Q DSI1
GOUT Q
G
Q DSI5
GOUT
G
Q DSI9
GOUT
G
Q DSI13
D
BBDLHS
D
BBDLHS
Q
D
BBDLHS
Q
D
BBDLHS
Q
GIN DOE1
G
HIGH SLEW
GIN DOE1 PAD
G
DOE2
HIGH SLEW
GIN
G
DOE2
HIGH SLEW
GIN
G
HIGH SLEW
2
DO2
D
E D Q
DSD2 DO6
D
E D Q
PAD
DSD6
DO10
D
E D Q
PAD
DSD10
DO14
D
E D Q
2 PAD DSD14
GOUT
G
Q DSI2
GOUT Q
G
Q DSI6
GOUT
G
Q DSI10
GOUT
G
Q DSI14
D
BBDLHS
D
BBDLHS
Q
D
BBDLHS
Q
D
BBDLHS
Q
GIN
G
DOE1
GIN
G
HIGH SLEW
GIN DOE2 PAD
G
DOE2
GIN
G
HIGH SLEW
DOE1
HIGH SLEW
DO3
D
E D Q
PAD
DO7 DSD3
D
E D Q
HIGH SLEW
DSD7 DO11
D
E D Q
PAD
DO15 DSD11
D
E D Q
PAD
DSD15
GOUT
GOUT G
Q DSI3 GIN
G
Q DSI7
GOUT Q
GOUT G
Q DSI11 GIN
G
Q DSI15 3
3
D
BBDLHS
Q
D
BBDLHS
D
BBDLHS
Q
D
BBDLHS
Q
GIN
G
G
DSI[7:0]
GIN
G
G
DSI[15:8]
DG1 DO[15:8] DO[7:0] DOE2 DG2 DOE1 GND GND
HIGH SLEW HIGH SLEW
DG2 DOE2
VCC Y
D
E D Q
D
PAD CPA0
E D Q
PAD
CPA1
VDD
4
GOUT
GOUT G
Q LA0 DG3 GIN
G
OUTBUF
D
BBDLHS
Q
D
BBDLHS
Q
Q
LA1
20CK
D
PAD
CLKOUT
IOPIL16 4
21 OCT 2002 DBS
D
4
DG3
GIN
G
G
DRAWN BY:
A
B
C
A
B
C
D
ENHD1 DSWDREG
A B
OR2A
Y
END1
1 DREG ENHD2 DOE1 PP4 CIQ[7:0] CIQ[7:0] CIQ[15:8] CIQ[15:8] HI[7:0] HI[7:0] HI[15:8] HIH[15:8] IQ[7:0] DSI[7:0] DSI[7:0] IQ[15:8] DSI[15:8] DSI[15:8] RA[1:0] 2 LA[1:0] LA[1:0] PP6 END1 END2 CLK PP6 END1 END2 CLK DATREG RA[1:0] IQ[15:8] DPNT1 DPNT0 IQ[7:0] SINT Q8 DOE1 PP4
1
A B
OR2A
Y
END2
A B
AND3
A B
NAND2B
Y
DPINC
Y
C
2
DCNT2
DSWST DPINC 3 Q8 CLK DSI[1:0]
SLOAD ENABLE ACLR CLOCK Q[1:0] DATA[1:0]
3 DPNT[1:0]
MXAD2
DATA0_[1:0] RESULT[1:0] DATA1_[1:0]
RA[1:0]
LA[1:0] LA0 LA1
SEL0
4
IOPIL16 5
PP6
4
22 OCT 2002
A B C
DRAWN BY: D
DBS
A REG1
B
C
D
HST[1:0] EN1 EN1 IQ[7:0] REG3 S CK 1 HI[7:0] A[7:0] Q[7:0] DSI[7:0] B[7:0] CLK DSI[7:2]
DATA[5:0] CLOCK Q[5:0]
MUX1
MUX2X8
DFME8
REG6
1 CIQ[7:0] DSWST
ENABLE
HST[7:0]
DATA0_[7:0] RESULT[7:0] DATA1_[7:0]
HO[7:0]
HST[7:2]
BUF1
SEL0
DSIW
A
BUF
Y
DSL EN2
REG2 EN1 DSWST
REG4
REG7
A
CLK
BUF2
BUF
Y
DSLA
S CK
DFME8 VDD CLK
ENABLE ACLR CLOCK Q[6:0]
HA0
HI[15:8] A[7:0] 2 DSI[15:8] B[7:0] Q[7:0] CIQ[15:8] DSI[14:8]
HST[14:8] 2
DATA[6:0]
HST14 MUX2 IQ[15:8]
MUX2X8
HICTLA ENHD1 ENHD2 HST[1:0] DPNT[1:0] SINT Q8 HSEL HWR 3 HRD HA0 HRD HA0 EN2 HRDY DSPINTR HCMDFL DSIW CLK DSIW CK HICTLA EN2 HST15 DSPINTR HCMDFL HA0 HSEL HWR EN1 EN1 SINT Q8 HST[15:8] ENHD1 ENHD2
DATA0_[7:0] RESULT[7:0] DATA1_[7:0]
HO[15:8]
SEL0
3
G2 G1 HWR 4 HSEL
A B
AND2B
A B
NAND2
Y
Y
HG1
D
DF1
Q
D
QN
DF1C
CLK
CLK
CLK
G3
HOST INTERFACE (HINTRFA)
24 OCT 2002
DRAWN BY: D
4
A B
NAND2
Y
HG2
DBS
A
B
C
A HRD HWR HRD HSEL
A
INV1
INV
B
C F13
D
Y A B C
HRD F1 F2 G1
OA1C
HCYC F3
J
D Y
DF1
Q
Q1
D
DF1
Q
Q2 GND
CLK
G2 1 HWR HSEL CK
CLK
Q1 HCYC
D0 D1 D2 D3
DFM6A
Q
HCYC
CK VDD
JKF2C
CS
Q
LWR
CLK K CLR
A B
AND2B
Y
HWR
S0 S1 CLK CLR
VCC Y
HSEL HWR
A B
AND2B
Y
1 SHWR F8 INV3 Q8 A
HCYC CK VDD G7 HSEL HWR HA0
J
JKF2C
CS
Q
INV
Y
HCMD
CLK K CLR
A B C
F9 HCYC CK VDD
AND3B
Y
SHCMD
J
JKF2C
CS
Q
INV4 Q9 A
INV
Y
LRDST
CLK K CLR
2
2
G10 HSEL HRD HA0
A B
AND3B
Y
SLRDST
C
INV2
A
HWR DSIW
INV
Y
DSPINTR G21
A B
NOR2
Y
HWR EN2 Q8
A B
NAND2
Y
ENHD2
A B
2
2
A B
NOR2
C Y
F5 EN1 F10
NOR4
CC
Y
HRDY
A B
NAND2
D Y
ENHD1
DF1
Q
D
DF1
Q
D
CLK
3 DPNT[1:0] DPNT0 DPNT1 LWR CK Q1
CLK A B C D
OA4
3
A B C A B
NAND2B NAND3B
Y
RDEN WREN Q8
A B C
SINT CLRFLGS
OR3C
Q2
Y
HCYC INTEN
Y
EBSY
A B C
AND3
Q9
Y
Y SINTR
F6
DSPINTR
J
JKF
Q
CLK K
LRDST HCYC
A B
AND2A
Y
G19 HCYC HCMD 4 CK DSIW
A B
AND2
Y
F7 HCCYC
J
JKF
Q
HCMDFL
CLK K
HICTLA
21 OCT 2002
DRAWN BY:
4
A
INV
Y
CLRFLGS
DBS
D
A
B
C
A
B
C
D
DSI[7:0]
DSI0
D
E
F0
DFE1B
Q
PNT0
A B C A
AND3B
Y
PP4 1
1
CLK
DSI1
D
E
F1
DFE1B
Q
PNT1
B C
AND3A
Y
PP6
CLK
DSI2 DSWPNT CLK
D
E
F2
DFE1B
Q
PNT2
CLK
DEC2 Y0 LA0 LR/W LA1 2 L1 R/W A E Y2 B Y3
DECE2X4D
G2 CPCYC ADW0
A B
NAND2
Y
DSWPNT
Y1 ADW2 ADW3 2
D
DL1B
Q
LR/W
DG3
G
G11 CPCYC1 PP4 ADW2 CPCYC1 PP4 ADW3
A B
AND3
Y
DSIW
G12
C A B C
AND3
Y
DSWST
3 VCC
ADW0 LR/W CPCYC1 Y F4 Q2 PP6
A B C D
AND4B
3
Y
DSWDREG
D
Q3
Q
DFE3A
E
CLK CLR
A
INV
Y
Q2 F5
A
Q3
BUF2
BUF
Y
CPCYC
A
INV
Y
GND
D0 D1 D2 D3
DFM6A
Q
A
BUF3
BUF
Y
CPCYC1
4 CPIS CPSTRB CPSEL CLK
CPS G6
A B C
Q3
AND3B
S0 S1 CLK CLR
Y
VCC Y
DSPWA
24 OCT 2002
DBS
D
4
CPS
DRAWN BY:
A
B
C
A
B
C
D
ST0
A
BUF
Y
CH0
1
ST15
A
BUF
Y
CH15
1
MUX2X16
CH15,GND,GND,GND[12:1],CH0
DATA0_[15:0]
DO[15:0]
RESULT[15:0]
IQ[15:0]
DATA1_[15:0]
A
2
BUF
Y
GND[12:1]
SEL0
$ARRAY=12
2
Y GND
LA0 LA1
A B
OR2
Y
IQSEL
3
3
4
DSPRA
24 OCT 2002
A B C
4
DRAWN BY: D
DBS
A
B
C
D
A[7:0]
B[7:0] 1 1
B0
A0
B1
A1
B2
A2
B3
A3
B4
A4
B5
A5
B6
A6
B7
A7
S EN1 CK
F0
F1
F2
F3
F4
F5
F6
F7
S E CLK
A B
S E CLK
A B
S E CLK
A B
S E CLK
A B
S E CLK
A B
S E CLK
A B
S E CLK
A B
S E CLK
A B
DFME1A
DFME1A
DFME1A
DFME1A
DFME1A
DFME1A
DFME1A
DFME1A
2
2
Q
Q0
Q
Q1
Q
Q2
Q
Q3
Q
Q4
Q
Q5
Q
Q6
Q
Q7 Q[7:0]
3
3
4
DFME8
4
19 NOV. 2002
A B C
DRAWN BY: D
DBS
A R1
B R5 EN1R1 EN1 EN1R3 DSPSEL S CK CK DFME8 DSPSEL2 S DFME8 EN1
C MUX1
MUX4X8
D
CIQ[7:0]
R1[7:0] R1[7:0] Q[7:0] HI[7:0] A[7:0] Q[7:0] DSI[7:0] B[7:0] R6 R3[7:0] R2[7:0] R3[7:0]
DATA0_[7:0] DATA1_[7:0] RESULT[7:0] DATA2_[7:0] DATA3_[7:0]
1
HI[7:0] A[7:0] DSI[7:0] B[7:0] R2 EN2R1 EN1 EN2R3 S CLK HIH[15:8] A[7:0] Q[7:0] DSI[15:8] B[7:0] DSI[15:8] B[7:0] R3 R1[15:8] HIH[15:8] A[7:0] Q[7:0] R3[15:8] MDS1 CK CLK DFME8 S CK DFME8 EN1
IQ[7:0]
1
SEL1
SEL0
MDS0
MUX2 LA0
2
A B C D
RA0
AND4A
MUX4X8
EN1R2
EN1 LA1 PP4
2
Y
DSIR
CIQ[15:8] R1[15:8]
DSPSEL1
S CK
DFME8 DOE1
DATA0_[7:0] DATA1_[7:0]
HI[7:0] A[7:0] Q[7:0] DSI[7:0] B[7:0] R4 Y EN2R2 EN1 GND R2[7:0]
A
S
MX2
RA1
A
S
MX2
IQ[15:8]
RESULT[7:0]
Y
MDS0 GND
Y
R2[15:8] MDS1 R3[15:8]
DATA2_[7:0] DATA3_[7:0]
GND
B
B
DEC1
DECE2X4 DATA0 EQ0 EQ1 EQ2
SEL1
SEL0
S CLK HIH[15:8] 3 DSI[15:8] B[7:0] A[7:0] CK
DFME8
DATA1
EN1R1 EN1R2 EN1R3 MDS1 MDS0 3
R2[15:8] Q[7:0]
EQ3
LA[1:0] B1
BUF
END1
ENABLE
PP6
A
Y
DSPSEL RA[1:0]
A
B2
BUF
Y
DSPSEL1 DEC2 RA0 DSPSEL2 RA1
DECE2X4 DATA0 DATA1 EQ0 EQ1 EQ2 EQ3
A
B3
BUF
Y
EN2R1 EN2R2 EN2R3
4
DATREG
END2
ENABLE
4
24 OCT 2002
A B C
DRAWN BY: D
DBS
6.3
8-bit Host Interface (IOPIL8)
This design implements a parallel interface with a host processor utilizing an 8-bit data bus. An understanding of the underlying operation of the design is only necessary if the designer intends to make modifications. In most cases this design can be implemented without changes. The following notes should be read while referencing the schematics. IOPIL16 1 is the top level schematic. The timing for the host to I/O chip communication can be found in section 4.4 and the timing for the CP to I/O chip communication can be found in section 4.7. The description below identifies the key elements of each schematic starting with the host side signals. The paragraph title identifies the key schematic(s) being described in the text. IOPIL8 3 The host interface for IOPIL8 is shown in sheet IOPIL8 3. The incoming data HD[7:0] is latched in the transparent latches when ~HG1 goes high. This would be a write from the host to the CP. The latched data HI[7:0] goes to IOPIL8 1 and IOPIL8 5. Data from the interface to the host, HO[7:0] is enabled onto the host bus, HD[7:0], by HOES1. The output latches, which present the data during a host read, are always transparent because GOUT is connected to VDD. The latched I/O is an I/O option on the Actel part used and could be omitted in the host interface if a different CPLD or FPGA does not have this feature. HD[15:8] are tri-stated outputs because Actel grounds unused I/O pins and this would interfere with using existing PMD test equipment. These reserved I/O's can be ommitted in a different implementation with an 8 bit bus. IOPIL8 1 The control for the host interface starts on IOPIL8 1. HOES1 is the AND of ~HSEL and ~HRD, and enable read data onto the host bus, as previously described. HRDY is a handshaking signal to the host to allow asynchronous communication between the host and the CP. The host must wait until HRDY is true before attempting to communicate with the CP. This signal is copied as a bit in the host status register. The host status register may be read at any time to determine the state of HRDY, or the HRDY output may be used as an interrupt to the host. ~HSEL, ~HRD, ~HWR, and HA0 are the buffered inputs of the host control signals. HOST INTERFACE/IOPIL8 5 Data from the host HI[7:0] is written into REG1 and REG2 on the schematic HOST INTERFACE by ~EN1 and ~EN2. All transfers are 16 bits and take two writes or reads on the 8-bit bus. These registers have a 2 to 1 multiplexed input with both the host data and the CP data being written to this register. This is convenient for diagnostic purposes and is very efficient in the Actel A42MX FPGA's, which are multiplexer based but if the configuration of the logic device used demands it, separate registers could be used for the host and CP data. The schematic for this register is shown as DFME8. Only commands and checksums are written to registers REG1 and REG2 while data is written and read from the set of data registers, DATREG shown on IOPIL8 5. These 3 data registers buffer data sent to and from the CP, reducing the number of interrupts the CP must handle. The output from REG1 and REG2, CIQ[15:8] and CIQ[7:0] go to IOPIL8 5, where they are multiplexed with the other data registers. The multiplexed result, IQ[15:8] and IQ[7:0], is multiplexed with HST[15:8] and HST[7:0] the output of the host status registers REG3 and REG4. This four input mux, MUX4X8, also muxes the 16 bit data onto the 8-bit bus. As previously mentioned HRDY becomes HST15 so it can be read by the host. The rest of the status register is written by the CP to provide information to the
MC3510 Technical Specifications 45
host. HA0 acts as an address bit, and usually is an address bit on the bus. When the host is writing, HA0 low indicates data and HA0 high indicates a command. When the host is reading, HAO low indicates data and HA0 high indicates status. Read status is the only transaction allowed while HRDY is low. During a host write the AND gate (G1:HOST INTERFACE) and two flops latch the incoming data in the interface latches by driving ~HG1 low from the start of the write transaction until the first negative clock transition after the first positive transition following the start of the write cycle. This tail-biting circuit removes the requirement for hold time on the data bus. HICTLA Most of the control logic for the host interface is shown on schematic HICTLA. The sequencer at the top generates HCYC one clock interval after the interface has been accessed and the host has finished the transaction. The nature of the transaction, rd/wr, command/data, and read status is preserved in the three flops F13, F8, and F9. Since 16 bit transfers must take place over an 8 bit bus two transfers are required. The toggle flop is used to determine whether a cycle is the first or second of the 2 required. The toggle flop may be initialized to the 0 state, which indicates that this is the first transfer (high byte), by the CP writing a one to host status bit 15. This status bit is read by the host as the HRDY bit and is not writable by the CP. In addition flop F12 and the associated gating determine if the present command transaction is the first or second byte of a command. If the toggle flop gets into the wrong state due to a missed or aborted transfer the next command will set it back to the correct state. A host write or a CP write, DSIW, enable REG1 and REG2 on the HOST INTERFACE schematic discussed previously. A host data write generates ~ENHD1 and ~ENHD2 for the data registers on the DATAREG schematic. For host writes ~EN2, ~EN1, ~ENHD2, and ~ENHD1 are also determined by the state of the toggle flop using HIEN and LOEN. 1CMD is used in this logic to ensure correct behavior when the command is correcting the state of the toggle. The logic at the bottom of the page generates the CP interrupt, the HRDY and the HCMDFL. The HCMDFL is used in the CP status to indicate a command. DSIW, the CP writing to REG1 and REG2 on the HOST INTERFACE schematic clears the interrupt and reasserts HRDY. HRDY is de-asserted during all host transactions except read status, and stays de-asserted until the CP has completed the DSIW cycle that clears the interrupt and reasserts HRDY. As mentioned previously data transfers to and from the host use the data registers and do not interrupt the CP. The CP knows the number of data transfers that must take place after decoding the command. It places this number, 0-3, in the 2 least significant bits of the host status register, HST[1:0]. These become DPNT[1:0] on this page of the schematic and enable an interrupt at 0 for a read and 1 or 0 for a write. The CP always leaves these bits at 0 unless setting up a multiple word data transfer. If INTEN is true and LRDST, latched read status, is false, HCYC will generate an interrupt to the CP. This will also hold HRDY false until after the CP writes to the interface register, DSIW, thereby generating ~CLRFLGS. IOPIL8 4 The CP interface is shown in sheet IOPIL8 4. The incoming data DSD[15:0] is latched in the transparent latches when ~DG1 and ~DG2 go high. This occurs at the completion of a write from the CP to the I/O chip. The latched data DSI[15:8] and DSI[7:0] go to schematic IOPIL8 1 and IOPIL16 5. DSI[7:0] also goes to IOPIL16 2. Data from the interface to the CP, DO[15:8] and DO[7:0] is enabled onto the CP bus, DSD[15:0], by DOE2 and DOE1 respectively. The output latches, which present the data during a CP read, are always transparent because GOUT is connected to VDD. The latched I/O in the Actel part contains both input and output latches. The output latches could be omitted in the CP interface if a different CPLD or FPGA does not have this feature. The two incoming CP address bits CPA0 and CPA1 are also latched using ~DG3. The 20CK signal is the clock for the CP. This is a 20 MHz clock derived from a 40 MHz clock input.
MC3510 Technical Specifications 46
IOPIL8 2 The CP control starts on IOPIL8 2. The I/O control is generated from ~CPSTRB, ~CPIS, CPSEL and R/W. ~DG1, ~DG2, and ~DG3 latch the incoming data and DOE1 and DOE2 out-enable the data from this chip to the CP. F2 and F4 tail-bite the write to avoid having to specify hold times on the data. Flop F1 divides the 40MHz clock down to 20 MHz. A 20 MHz clock could be used for this interface and the CP. DSPWA The CP write control is contained on schematic DSPWA. The CP interface uses page addressing to save I/O pins. F0, F1 and F2 make up the page register. In addition there are the 2 address bits, LA0 and LA1. A write to address 0 selects the page register with DSI[2:0] going to the page register and selecting the page for the successive transfers. A read from address 0 reads the status register on all pages. Pages 4 and 6 are the only ones implemented in this device. L1 latches the r/w level. The write decoding generates DSIW which enables writes to the DFME8 registers reg1 and reg2 shown on the HOST INTERFACE schematic. DSIW also clears the CP interrupt and restores HRDY. DSWST writes to the host status register also shown on the HOST INTERFACE schematic. DSWDREG implements writing to the data registers shown on IOPIL8 5 and DATREG. Finally the logic at the bottom of the page generates CPCYC, a 1-clock interval after the CP cycle is over that implements the actual writes to the registers. The use of the data bus latches and the post bus cycle transfers keeps as much of the logic synchronous as possible given two asynchronous devices, without requiring clocking at several times the bus speed. DSPRA The CP read control is contained on schematic DSPRA. The 2 by 16 bit mux selects CP status if the CP latched address is 0 and IQ[15:0] if the address is not 0. The only significant status bits are bits 15 (indicating the CP is interrupting the host), bit 14 (1 indicating an 8-bit host interface) and bit 0 (set to 1 during a host command transfer and 0 during data transfer). HOST INTERFACE Both the CP and the host use a special mode to transfer data to avoid unnecessary CP interrupts. This special mode is under the control of the CP and is transparent to the host. When the CP receives a command from the host it initializes the transfer by setting the number of transfers expected (0,1,2 or 3) in the 2 LSB's of the host status register, REG3 and REG4 on HOST INTERFACE. This write (DSWST) also loads these bits into the 2 bit down counter DCNT2 on IOPIL8 5. Note that a Q8 low, which indicates a host command, asynchronously clears this register enabling interrupts on schematic HICTLA. If DPNT[1:0] is not 0 and Q8 is high, indicating a host data transfer, and SINT goes high indicating the end of a host cycle the counter is decremented. MXAD2 selects address RA from the CP latched address bits if the page register contains 6, or the counter contents DPNT[1:0] if not. This allows the CP to have direct access to registers 1, 2, and 3, using address 1,2,and 3 on page 6. The host on the other hand can only read or write to the data register, HA0 low and the counter will auto decrement from 3 down to 0 allowing the host to access the registers on DATAREG where REG1=R1 and R2, REG2=R3 and R4, and REG3=R5 and R6. The writes are enabled by the two decoders DECE2X4 while the reads are selected by the two 4x8 muxes, MUX1 and MUX2 controlled by the two 2x1 muxes MDS1 and MDS0. The output data IQ[15:0] goes to HOST INTERFACE schematic below IOPIL8 1 and to DSPRA below IOPIL8 2. The write data is HI[7:0] from the host and DSI[15:8] and DSI[7:0] from the CP. Note that END1
MC3510 Technical Specifications 47
and END2, the write enables, are both high for DSWDREG, while they are high one at a time for host writes controlled by the toggle flop. SINT enables DPINC only when the toggle is high after the second transfer.
MC3510 Technical Specifications 48
A
B
C
D
HINTF HSTSEL
PAD
INBUF
IN17
Y
HSEL
HSEL HRD
HOST INTERFACE (HINTRFA) HO[7:0] HO[7:0] 1
HSTRD 1
PAD
INBUF
IN18
Y
HWR HRD HA0
HSTWR
PAD
INBUF
IN19
Y
HI[7:0] HWR HI[7:0]
HADR0
PAD
INBUF
IN20
Y
HA0
DSI[15:8] DSI[15:8] DSI[7:0] DSI[7:0] DPNT[1:0] HST[1:0] Q8 DSWST DSIW DSWST SINT DSIW CIQ[15:8] CIQ[7:0]
CIQ[7:0] CIQ[15:8]
Q8
SINT
2
HG1 IQ[7:0] IQ[7:0] HST14 IQ[15:8] IQ[15:8] HCMDFL DSPINTR CLK CLK HST15 ENHD1 ENHD2 HRD HSEL
HG1
2
ST15 ST0 DSPINTR
OUTBUF
RDY ENHD1 ENHD2
D
PAD
HRDY
A B
AND2B
Y
HOES1
3
3
OUTBUF
DSPINTR
D
OUT5
PAD
DSPINT
4
IOPIL8 1
22 OCT 2002
A B C DRAWN BY: D
4
DBS
A
B
C
D
PNT0 PNT1
CSEL0 CSEL1 ST0 DSPRA ST0 1 ST15 ST15 IQ[15:0]
DSWDREG 1 DSI[7:0] DSI[7:0] DSWST PP4 PP6 DSIW
DSWDREG
DSIW DSWST PP4 PP6
IQ[15:0]
IN27 CS
PAD
INBUF
Y
DG3 IN28 DG3 DO[15:0] DO[15:0] LA0 IN26 LA0 LA1 2 CPSEL R/W CPSTRB CPSEL R/W LA0 CPSTRB LA1 LA1 DSPRA CLK CLK DSPWA CLKINT CPIS CPCYC CPCYC LA0
CPR-W
PAD
INBUF
Y
2
STRB
PAD
INBUF
Y
IN30
LA1
IS
PAD
INBUF
Y
CKBUF 20CK
CPIS
A
Y
CPSTRB CPIS CPSEL
A B C
G1
NAND3B
Y
CSACC
A B
R/W 3 G2
AND4B
C D A B C D
Y
F1 DOE1 IB1 CLKIN
INBUF
D PAD Y
40CK
QN
DF1A
20CK 3
CLK
G3
AND4B
Y
DOE2
A B C
G4
NAND3B
Y
DG1
A B
4
G5 F2
NAND3B
F4
Y
CSACC DG2
D
DF1
Q
CQ1
D
DF1
Q
CQ3
C A
CSACC CQ3
CLK B C D
G6
NAND4B
CLK
IOPIL8 2
30 OCT 2002
DRAWN BY: D
4
Y
CLK DG3
DBS
A
B
C
A
B
C
D
HIGH SLEW
HO0
D
E D Q
PAD
HIGH SLEW
HD0 HO4
D
E D Q
PAD
HD4
GOUT
1
D G
Q HI0 VDD
E
TRIBUFF
PAD
HD8 1
GOUT
G
Q HI4
VDD GIN
D
BBDLHS
Q
D
BBDLHS
Q
D
E
TRIBUFF
PAD
HD9
G
GIN
G D
PAD HD5
HIGH SLEW
HO1
D
E D Q
PAD
HIGH SLEW
E
TRIBUFF
PAD
HD10
HD1 HO5
D
E D Q
GOUT
G
Q HI1
GOUT Q
G
Q HI5
D Q
E
TRIBUFF
PAD
HD11
D
BBDLHS
D
BBDLHS
GIN 2 HO2
G
HIGH SLEW
GIN
G
HIGH SLEW
D
E
TRIBUFF
PAD
HD12 2
D
E D Q
PAD
HD2 HO6
D
E D Q
PAD
HD6
GOUT
D G
Q HI2
E
TRIBUFF
PAD
HD13
GOUT Q
G
Q HI6
D
BBDLHS
D
BBDLHS
Q
D
E
TRIBUFF
PAD
HD14
GIN
G
GIN
G
HIGH SLEW
HIGH SLEW
HO3
D
E D Q
PAD
HD3
HO7
D
E D Q
D
PAD HD7
E
TRIBUFF
PAD
HD15
GOUT
3
G
Q HI3
GOUT
G
Q HI7
Y GND 3
D
BBDLHS
Q
D
BBDLHS
Q
GIN
G
GIN
HI BYTE TRISTATE TO HI[7:0] AVOID LOADING 16 BIT BUSSES
G
HG1 HO[7:0]
HG1
VCC HOES1 Y VDD 4
IOPIL8 3
24 OCT 2002
A B C DRAWN BY:
4
DBS
D
A DOE1
HIGH SLEW
B
C
D
DOE1 PAD
HIGH SLEW
DOE2
HIGH SLEW
DOE2
HIGH SLEW
DO0
D
E D Q
DSD0 DO4
D
E D Q
PAD
DSD4
DO8
D
E D Q
PAD
DSD8
DO12
D
E D Q
PAD
DSD12
VDD 1
GOUT
G
Q DSI0
VDD
GOUT
G
Q DSI4
VDD
GOUT
G
Q DSI8
VDD
GOUT
G
1 Q DSI12
D
BBDLHS
Q
D
BBDLHS
Q
D
BBDLHS
Q
D
BBDLHS
Q
GIN DOE1
G
DOE1 PAD
GIN
G
DOE2
HIGH SLEW
GIN
G
DOE2
HIGH SLEW
GIN
G
HIGH SLEW
DO1
D
E D Q
HIGH SLEW
DSD1 DO5
D
E D Q
PAD
DSD5
DO9
D
E D Q
PAD
DSD9
DO13
D
E D Q
PAD
DSD13
GOUT
G
Q DSI1
GOUT Q
G
Q DSI5
GOUT
G
Q DSI9
GOUT
G
Q DSI13
D
BBDLHS
D
BBDLHS
Q
D
BBDLHS
Q
D
BBDLHS
Q
GIN DOE1
G
HIGH SLEW
GIN DOE1 PAD
G
DOE2
HIGH SLEW
GIN
G
DOE2
HIGH SLEW
GIN
G
HIGH SLEW
2
DO2
D
E D Q
DSD2 DO6
D
E D Q
PAD
DSD6
DO10
D
E D Q
PAD
DSD10
DO14
D
E D Q
2 PAD DSD14
GOUT
G
Q DSI2
GOUT Q
G
Q DSI6
GOUT
G
Q DSI10
GOUT
G
Q DSI14
D
BBDLHS
D
BBDLHS
Q
D
BBDLHS
Q
D
BBDLHS
Q
GIN
G
DOE1
GIN
G
HIGH SLEW
GIN DOE2 PAD
G
DOE2
GIN
G
HIGH SLEW
DOE1
HIGH SLEW
DO3
D
E D Q
PAD
DO7 DSD3
D
E D Q
HIGH SLEW
DSD7 DO11
D
E D Q
PAD
DO15 DSD11
D
E D Q
PAD
DSD15
GOUT
GOUT G
Q DSI3 GIN
G
Q DSI7
GOUT Q
GOUT G
Q DSI11 GIN
G
Q DSI15 3
3
D
BBDLHS
Q
D
BBDLHS
D
BBDLHS
Q
D
BBDLHS
Q
GIN
G
G
DSI[7:0]
GIN
G
G
DSI[15:8]
DG1 DO[15:8] DO[7:0] DOE2 DG2 DOE1 GND GND
HIGH SLEW HIGH SLEW
DG2 DOE2
VCC Y
D
E D Q
D
PAD CPA0
E D Q
PAD
CPA1
VDD
4
GOUT
GOUT G
Q LA0 DG3 GIN
G
OUTBUF
D
BBDLHS
Q
D
BBDLHS
Q
Q
LA1
20CK
D
PAD
CLKOUT
IOPIL8 4
22 OCT 2002
DRAWN BY: D
4
DG3
GIN
G
G
DBS
A
B
C
A
B
C
D
ENHD1 DSWDREG
A B
OR2A
Y
END1
1 DREG ENHD2 DOE1 PP4 CIQ[7:0] CIQ[7:0] CIQ[15:8] CIQ[15:8] HI[7:0] HI[7:0] SINT IQ[7:0] IQ[7:0] DSI[7:0] DSI[7:0] IQ[15:8] DSI[15:8] DSI[15:8] RA[1:0] 2 LA[1:0] LA[1:0] PP6 END1 END2 CLK PP6 END1 END2 CLK DATREG RA[1:0] IQ[15:8] DPNT1 DPNT0 Q8 DOE1 PP4
1
A B
OR2A
Y
END2
A B
AND3
A B
NAND2B
Y
DPINC
Y
C
2
DCNT2
DSWST DPINC 3 Q8 CLK DSI[1:0]
SLOAD ENABLE ACLR CLOCK Q[1:0] DATA[1:0]
3 DPNT[1:0]
MXAD2
DATA0_[1:0] RESULT[1:0] DATA1_[1:0]
RA[1:0]
LA[1:0] LA0 LA1
SEL0
4
IOPIL8 5
PP6
4
22 OCT 2002
A B C
DRAWN BY: D
DBS
A REG1
B
C
D
HST[1:0] EN1 EN1
MUX4X8
REG3 S CK 1 HI[7:0] A[7:0] Q[7:0] DSI[7:0] B[7:0] CLK DSI[7:2]
DATA[5:0] CLOCK Q[5:0]
DFME8
REG6
IQ[7:0] 1
CIQ[7:0]
DSWST
ENABLE
HST[7:0]
DATA0_[7:0] DATA1_[7:0] RESULT[7:0]
HO[7:0]
IQ[15:8] HST[7:2] HST[15:8]
DATA2_[7:0] DATA3_[7:0]
BUF1 DSIW
A
BUF
Y
DSL EN2
REG2 EN1 DSWST
REG4
SEL1 SEL0
REG7
A
CLK
BUF2
BUF
Y
DSLA
S CK
DFME8 VDD CLK
ENABLE ACLR CLOCK Q[6:0]
TOGGLE A HST[14:8] HA0
INV
Y
HI[7:0] A[7:0] 2 DSI[15:8] B[7:0] Q[7:0] CIQ[15:8] DSI[14:8]
TOGGLE LO
DATA[6:0]
2
SELECTS [15:8], HI BYTE FIRST
HST14
DSWST DSI15
A B
NAND2
Y
RSTOG
HICTLA ENHD1 ENHD2 HST[1:0] DPNT[1:0] RSTOG 3 HSEL HWR HRD HA0 RSTOG HSEL HWR HRD HA0 SINT Q8 TOGGLE EN1 EN2 HRDY DSPINTR HCMDFL DSIW CLK DSIW CK HICTLA SINT Q8 TOGGLE EN1 EN2 HST15 DSPINTR HCMDFL 3 ENHD1 HST[15:8] ENHD2
G2 G1 HWR 4 HSEL
A B
NAND2
Y
HG1
A B
AND2B
Y
D
DF1
Q
D
QN
DF1C
CLK
CLK
CLK
HOST INTERFACE (HINTRFA)
24 AUG 2001
DRAWN BY: D
4
DBS
A
B
C
A HRD HWR HRD HSEL 1 HWR HSEL CK
B
C F13
D
A
INV1
INV
Y
HRD F1 F2 G1
OA1C
HCYC F3
J
A B C
G2
D Y
DF1
Q
Q1
D
DF1
Q
Q2 GND
CLK Y
HWR
CLK
Q1 HCYC
D0 D1 D2 D3
DFM6A
Q
HCYC
CK VDD
JKF2C
CS
Q
LWR
CLK K CLR
A B
AND2B
S0 S1 CLK CLR
VCC Y
HSEL HWR
A B
AND2B
Y
1 SHWR F8 INV3 Q8 A
HCYC CK VDD 1CMD F4 TOGGLE
J
JKF2C
CS
Q
INV
Y
HCMD
CLK K CLR
A B
NAND2A
Y
G7 HSEL HWR
A B C
F9 HCYC CK VDD
AND3B
Y
SHCMD
D
HCYC CK
Q
DFE3A
HA0
E
A
LCMD
CLK CLR
F12 RSTOG Q8 HCYC
B
AND2A
Y
1CMD
J
JKF2C
CS
Q
INV4 Q9 A
INV
Y
LRDST
CLK K CLR
2
2 TOGGLE LO (1ST BYTE) LD HI, RD HI
D E
DFE
Q
HSEL HRD HA0
G10
A B
CK
CLK
AND3B
Y
SLRDST
C
INV2 G12 TOGGLE 1CMD HWR
OR2A
A B
A B
HIEN HWR
AOI1
A B C
NAND3
A Y
ENHD2
INV
Y
DSPINTR G21
Y
HIEN DSIW
C
Y EN2
Q8
A B
2
2
LOEN G14 1CMD TOGGLE 3 DPNT[1:0] DPNT0 DPNT1 LWR HWR
AND2A
A B C
NAND3
C
F5 F10
NOR4
CC
Y
HRDY
Y
A B
A B
ENHD1
D
DF1
Q
D
DF1
Q
D
Y
LOEN DSIW
C
AOI1
Y EN1
CK
CLK
Q1
CLK A B C D
OA4
3
A B C A B
NAND2B NAND3B
Y
RDEN WREN Q8
A B C
SINT CLRFLGS
OR3C
Q2
Y
HCYC INTEN
Y
EBSY
A B C
AND3
Q9
Y
Y SINTR
F6
J
JKF
Q
DSPINTR
CLK K
LRDST 1CMD TOGGLE
A B C
AND3A
A B
AND2A
HCYC
Y
Y
ENINTR
G19 HCYC HCMD 4 CK DSIW
A B
AND2
Y
F7 HCCYC
J
JKF
Q
HCMDFL
CLK K
HICTLA
22 OCT 2002 DBS
D
4
A
INV
Y
CLRFLGS
DRAWN BY:
A
B
C
A
B
C
D
DSI[7:0]
DSI0
D
E
F0
DFE1B
Q
PNT0
A B C
1
AND3B
Y
PP4
1 DSI1
CLK
F1
DFE1B
D
E
Q
PNT1
A B C
AND3A
Y
PP6
CLK
DSI2 DSWPNT CLK
D
E
F2
DFE1B
Q
PNT2 G2 CPCYC DEC2 Y0 LA0 LR/W LA1 A E Y2 B Y3
DECE2X4D
A B
NAND2
CLK
ADW0
Y
DSWPNT
Y1 ADW2 ADW3
L1 R/W 2 DG3
D
DL1B
Q
LR/W 2 G11 CPCYC1 PP4 ADW2
G
A B
AND3
Y
DSIW
C
G12 CPCYC1 PP4 ADW3
A B
AND3
Y
DSWST
C
ADW0 LR/W CPCYC1 3 VCC Y F4 Q2 PP6
A B C D
AND4B
Y
DSWDREG 3
D
Q3
Q
DFE3A
E
CLK CLR
A
INV
Y
Q2 F5
A
Q3
BUF2
BUF
Y
CPCYC
A
INV
Y
GND
D0 D1 D2 D3
DFM6A
Q
A
BUF3
BUF
Y
CPCYC1
4 CPIS CPSTRB CPSEL CLK
CPS G6
A B C
Q3
AND3B
S0 S1 CLK CLR
Y
VCC Y
DSPWA
24 OCT 2002
DBS
D
4
CPS
DRAWN BY:
A
B
C
A
B
C
D
VCC Y CH0 VDD 1 ST15
ST0 1
A
BUF
Y
A
BUF
Y
CH15
MUX2X16
CH15,VDD,GND,GND[12:1],CH0
A
BUF
Y
GND[12:1]
DATA0_[15:0] RESULT[15:0]
DO[15:0]
$ARRAY=12 GND IQ[15:0]
DATA1_[15:0]
SEL0
2 Y GND
2
LA0 LA1
A B
OR2
Y
IQSEL
3
3
4
DSPRA
30 OCT 2002
A B C
4
DRAWN BY: D
DBS
A
B
C
D
A[7:0]
B[7:0] 1 1
B0
A0
B1
A1
B2
A2
B3
A3
B4
A4
B5
A5
B6
A6
B7
A7
S EN1 CK
F0
F1
F2
F3
F4
F5
F6
F7
S E CLK
A B
S E CLK
A B
S E CLK
A B
S E CLK
A B
S E CLK
A B
S E CLK
A B
S E CLK
A B
S E CLK
A B
DFME1A
DFME1A
DFME1A
DFME1A
DFME1A
DFME1A
DFME1A
DFME1A
2
2
Q
Q0
Q
Q1
Q
Q2
Q
Q3
Q
Q4
Q
Q5
Q
Q6
Q
Q7 Q[7:0]
3
3
4
DFME8
4
19 NOV. 2002
A B C
DRAWN BY: D
DBS
A R1
B R5 EN1R1 EN1 EN1R3 DSPSEL S CK CK DFME8 DSPSEL2 S DFME8 EN1
C MUX1
MUX4X8
D
CIQ[7:0] R1[7:0] R1[7:0] Q[7:0] DSI[7:0] B[7:0] R2 R6 EN2R1 EN1 EN2R3 S CLK HI[7:0] A[7:0] Q[7:0] DSI[15:8] B[7:0] DSI[15:8] B[7:0] R3 2 EN1R2 EN1 LA0 LA1 DSPSEL1 S CK HI[7:0] A[7:0] Q[7:0] DSI[7:0] B[7:0] R4 EN2R2 EN1 DSIR S CLK HI[7:0] 3 DSI[15:8] B[7:0] Y GND PP6 A[7:0] Q[7:0] R2[15:8] GND CK
MX2 MX2
DATA0_[7:0] DATA1_[7:0]
1
HI[7:0] A[7:0] HI[7:0] A[7:0] Q[7:0] DSI[7:0] B[7:0] R3[7:0] R3[7:0] R2[7:0]
IQ[7:0]
RESULT[7:0]
1
DATA2_[7:0] DATA3_[7:0]
EN1
SEL1 SEL0
DFME8 CK CLK R1[15:8] HI[7:0] A[7:0] Q[7:0] R3[15:8] MDS1 S CK DFME8
MDS0
MUX2
MUX4X8
A B C D
RA0
AND4A
2
Y
CIQ[15:8] DSIR R1[15:8]
DATA0_[7:0] DATA1_[7:0]
DFME8
PP4 DOE1 R2[7:0]
IQ[15:8]
RESULT[7:0]
A
S Y
MDS0
R2[15:8] R3[15:8]
DATA2_[7:0] DATA3_[7:0]
GND
B
SEL1
SEL0
DFME8 RA1
A
S Y
MDS1 MDS1 MDS0 3
B
A
B1
BUF
Y
DSPSEL
LA[1:0]
DECE2X4
A
B2
BUF
Y
DSPSEL1 END1
DATA0 ENABLE DATA1
EQ0 EQ1 EQ2 EQ3 EN1R1 EN1R2 EN1R3
A
B3
BUF
Y
DSPSEL2 RA[1:0]
DECE2X4
4
RA0 END2 RA1
DATA0 ENABLE DATA1
EQ0 EQ1 EQ2 EQ3 EN2R1 EN2R2 EN2R3
DATREG
4
30 OCT 2002
A B C
DRAWN BY: D
DBS
7 Application Notes
7.1 Design Tips
The following are recommendations for the design of circuits that utilize a PMD Motion Processor. Serial Interface If the serial configuration decode logic is not implemented (see section 7.2) the CP data bus should be tied high. This places the serial interface in a default configuration of 9600,n,8,1 after power on or reset. Controlling pulse output during reset When the motion processor is in a reset state (when the reset line is held low) or immediately after a power on, the pulse outputs can be in an unknown state, causing undesirable motor movement. It is recommended that the enable line of any motor amplifier be held in a disabled state by the host processor or some logic circuitry until communication to the motion processor is established. This can be in the form of a delay circuit on the amplifier enable line after power up, or the enable line can be ANDed with the CP reset line. Parallel word encoder input When using parallel word input for motor position, it is useful to also decode this information into the User I/O space. This allows the current input value to be read using the chip instruction ReadIO for diagnostic purposes. Using a non standard system clock frequency It is often desirable to share a common clock among several components in a design. In the case of the PMD Motion Processors it is possible to use a clock below the standard value of 20MHz. In this case all system frequencies will be reduced as a fraction of the input clock verses the standard 20MHz clock. The list below shows the affected system parameters:* * * * Serial baud rate Maximum pulse rate Timing characteristics as shown in section 3.2 Cycle time
For example, if an input clock of 17MHz is used with a serial baud rate of 9600 the following timing changes will result:* * * Serial baud rate decreases to 9600 bps *17/20 = 8160 bps Maximum step rate decreases to 50K pulses *17/20 = 42.5K pulses Cycle time per axis increases to 102.4 sec *20/17 = 120.48 sec
MC3510 Technical Specifications 60
MC3510 Technical Specifications 61
7.2
RS-232 Serial Interface
The interface between the MC3510 chip and an RS-232 serial port is shown in the following figure. Comments on Schematic S1 and S2 encode the characteristics of the serial port such as baud rate, number of stop bits, parity, etc. The CP will read these switches during initialization, but these parameters may also be set or changed using the SetSerialPort chipset command. The DB9 connector wired as shown can be connected directly to the serial port of a PC without requiring a null modem cable.
MC3510 Technical Specifications 62
8
7
6
5
4
3
2
1
R? VCC DS[0..15]
D
RS1 A[0..15] U1 110 111 112 114 115 116 117 118 119 122 123 124 125 126 127 128 131 129 130 4 6 1 132 98 NOT 105 106 107 U2 STRB2 NOT SRLRCV SRLXMT SRLENABLE I/OINTRPT PRLENABLE ANALOG1 ANALOG2 ANALOG3 ANALOG4 ANALOG5 ANALOG6 ANALOG7 ANALOG8 ANALOGVCC ANALOGREFHIGH ANALOGREFLOW ANALOGGND 43 44 99 53 65 74 89 75 88 76 83 77 82 84 85 86 87 C1 .1UF 50V C1+ C1C2+ C2C2 .1UF 50V SERXMIT SERRCV 1 3 4 5 11 10 12 9 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 ISR/W STRBIS2 COM R1 R2 R3 R4 R5 R6 R7 R8 RSIP9 S1 1 2 3 4 5 6 7 8 SW DIP-8 16 15 14 13 12 11 10 9 SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8 2 4 6 8 11 13 15 17 1 19 U2 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1G 2G 74LS244 U2 U2 AND U3 COULD BE IMPLEMENTED IN A PLD 1 A9 R/W 2 3 4 5 NAND4 U2 1 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 18 16 14 12 9 7 5 3 DS0 DS1 DS2 DS3 DS4 DS5 DS6 DS7 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 VCC SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8
RS2 COM R1 R2 R3 R4 R5 R6 R7 R8 RSIP9 S2 16 15 14 13 12 11 10 9 SW DIP-8 SW9 SW10 SW11 SW12 SW13 SW14 SW15 SW16 2 4 6 8 11 13 15 17 1 19 U3 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1G 2G 74LS244 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 18 16 14 12 9 7 5 3 DS8 DS9 DS10 DS11 DS12 DS13 DS14 DS15 1 2 3 4 5 6 7 8 9 VCC SW9 SW10 SW11 SW12 SW13 SW14 SW15 SW16
~RS VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
35 2 7 13 21 36 40 47 50 52 60 62 93 103 121
22K
DS0 DS1 DS2 DS3 DS4 DS5 DS6 DS7 DS8 DS9 DS10 DS11 DS12 DS13 DS14 DS15
9 10 11 12 15 16 17 18 19 22 23 24 25 26 27 28 63 64
DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 POSLIM1 NEGLIM1 AXISIN1 AXISOUT1 QUADA1 QUADB1 ~INDEX1 ~HOME1
ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 N/C ~RAMSLCT ~PERIPHSLCT R/~W ~STROBE ~WRITEENBL W/~R
DS[0..15]
DS[0..15]
D
C
72 94 67 68 69 70
C
~HOSTINTRPT DIRECTION1 PULSE1 ATREST1
VCC
U3 C1+ C1C2 C2T1IN T2IN R1OUT R2OUT V+ VT1OUT T2OUT R1IN R2IN 2 6 14 7 13 8 V+ VTXD RXD
C3 .1UF 50V
C5 .1UF 50V
C4 .1UF 50V J1 GND 5 9 4 8 3 7 2 6 1 CONNECTOR DB9 FEMALE DB9 WIRED AS SHOWN WILL CONNECT TO A PC WITHOUT A DUMMY MODEM.
B
B
AD232
RSCLK
41 58
CLOCKIN
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND CP2N11 GND
~RESET
A
3 8 14 20 29 37 46 56 59 61 71 92 104 113 120
A
PERFORMANCE MOTION DEVICES 55 OLD BEDFORD RD LINCOLN, MA 01773 Title RS232 SERIAL INTERFACE Size B Date:
8 7 6 5 4 3
Document Number Monday, July 07, 2003
2
Rev B Sheet 1 of
1
0
7.3
RS 422/485 Serial Interface
The interface between the MC3510 chip and an RS-422/485 serial port is shown in the following figure. Comments on Schematic Use the included table to determine the jumper setup that matches the chosen configuration. If using RS485, the last CP must have its jumpers set to RS485 LAST. The DB9 connector wiring is for example only. The DB9 should be wired according to the specification that accompanies the connector to which it is attached. For correct operation, logic should be provided that contains the start up serial configuration for the motion processor. Refer to the RS232 Serial Interface schematic for an example of the required logic. Note that the RS485 interface cannot be used in point to point mode. It can only be used in a multidrop configuration where the chip SrlEnable line is used to control transmit/receive operation of the serial transceiver. Chips in a multi-drop environment should not be operated at different baud rates. This will result in communication problems.
MC3510 Technical Specifications 64
8
7
6
5
4
3
2
1
TX-RX +
D
TERMINATE TRANSMIT TXT JP1 1 JMP3 3 2
D
JP3 1 JMP3 3 2
VCC R3 4.7K 14 U1 Y Z 9 10 TX+ TX5 9 4 8 3 7 2 6 1 R1 120 P1
SRLXMT SRLRCV SRLENABLE GND
C
5 4 3 C1 + 4.7UF 10V TANT C2 .1UF 50V CER 2
DI DE RE
VCC
GND
GND
VCC
A B
12 11 MAX491
RX+ RX-
TO HOST
C
RO
CONNECTOR DB9 RT ANGLE MALE
6 GND
7
R2 120 JP4 1 JMP3 TX-RX B
3 2
RXT
JP2 1 JMP3 TERMINATE RECEIVE 3 2
B
COM TYPE
JP1
JP2
JP3
JP4
RS422
1-2
1-2
2-3
2-3
RS485
2-3
2-3
1-2
1-2
RS485 LAST
1-2
2-3
1-2
1-2
NOTE:RS422 IS CAPABLE OF FULL DUPLEX AND USES 2 PAIRS. RS485 IS HALF-DUPLEX ON 1 PAIR AND MAY BE DAISY CHAINED
A
THE CP USES RS485. A SINGLE CP MAY COMMUNICATE WITH AN RS422 HOST AS SHOWN IN THE TABLE. A SINGLE PAIR MAY BE WIRED TO EITHER P1-1,9 OR P1-2,3 Title FOR RS485. Size B Date:
8 7 6 5 4 3
A
PERFORMANCE MOTION DEVICES 55 OLD BEDFORD RD LINCOLN, MA 01773 RS422/485 Interface Document Number Thursday, April 11, 2002
2
Rev A Sheet 1
1
of
1
7.4
RAM Interface
The following schematic shows an interface circuit between the MC3510 and external ram. Comments on Schematic The CP is capable of directly addressing 32K words of 16-bit memory. It will also use a 16 bit paging register to address up to 32K word pages. The schematic shows the paging and addressing for 128KB RAM chips, i.e. 4 pages per RAM chip. The page address decoding is shown for only 6 of the 16 possible paging bits. The decoding time from W/R and DS- to the memory output must not exceed 18 ns. for a read with no wait states. The writes provide 25 extra ns access time for W/R and DS- to reverse the CP data bus.
MC3510 Technical Specifications 66
8
7
6
5
4
3
2
1
D[0..15]
A[0..14]
D
R? VCC 22K 35 2 7 13 21 36 40 47 50 52 60 62 93 103 121 VCC U? U2 110 111 112 114 115 116 117 118 119 122 123 124 125 126 127 128 131 129 130 4 6 1 132 98 105 106 107 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 DSISR/W W EW/R D0 D1 D2 D3 D4 D5 D6 D7 W EPGR3 4 7 8 13 14 17 18 11 1 D1 D2 D3 D4 D5 D6 D7 D8 CLK G 74LS377 GND Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 2 5 6 9 12 15 16 19 MPG0 MPG1 2 3 1 U2A A B G POS139 U2B 14 13 15 A B G POS139 U2 D8 D9 D10 D11 D12 D13 D14 D15 W EPGR3 4 7 8 13 14 17 18 11 1 D1 D2 D3 D4 D5 D6 D7 D8 CLK G 74LS377 PAGE REGISTER UP TO 16 BITS SRLRCV SRLXMT SRLENABLE I/OINTRPT PRLENABLE ANALOG1 ANALOG2 ANALOG3 ANALOG4 ANALOG5 ANALOG6 ANALOG7 ANALOG8 ANALOGVCC ANALOGREFHIGH ANALOGREFLOW ANALOGGND RSCLK 41 58 ~RESET CLOCKIN 43 44 99 A13 53 65 NOT OR3 74 89 75 88 76 83 77 82 84 85 86 87 2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 MPG0 MPG1 DSCS2 WEW/R 12 11 10 9 8 7 6 5 27 26 23 25 4 28 3 31 2 22 30 29 24 U? A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 CE1 CE2 WE OE MCM6226 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 13 14 15 17 18 19 20 21 D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 MPG0 MPG1 DSCS2 WEW/R 12 11 10 9 8 7 6 5 27 26 23 25 4 28 3 31 2 22 30 29 24 U? A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 CE1 CE2 WE OE MCM6226 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 13 14 15 17 18 19 20 21 D8 D9 D10 D11 D12 D13 D14 D15 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 2 5 6 9 12 15 16 19 NOTE:THE CRITICAL DECODE AND MEMORY ACCESS TIME IS DURING READ, THE REQUIRED ACCESS TIME IS 18 NS. FROM DS- LOW. AS ILLUSTRATED THERE IS ~ 100NS. TO ACCOMPLISH THE DECODING FROM PAGE REG WRITE TO MEMORY READ OR WRITE. DECODING WILL HAVE TO BE CAREFULLY DONE ON MEMORIES WITH A SINGLE CHIP SELECT. Y0 Y1 Y2 Y3 12 11 10 9 CS5 CS6 CS7 CS8 Y0 Y1 Y2 Y3 4 5 6 7 CS1 CS2 CS3 CS4 NOTE: POS139 IS A STANDARD 139 WITH INVERTED OUTPUTS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 MPG0 MPG1 DSCS1 WEW/R 12 11 10 9 8 7 6 5 27 26 23 25 4 28 3 31 2 22 30 29 24 U? A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 CE1 CE2 WE OE MCM6226 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 13 14 15 17 18 19 20 21 D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 MPG0 MPG1 DSCS1 WEW/R 12 11 10 9 8 7 6 5 27 26 23 25 4 28 3 31 2 22 30 29 24 U? A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 CE1 CE2 WE OE MCM6226 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 13 14 15 17 18 19 20 21 D8 D9 D10 D11 D12 D13 D14 D15
D
C
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
9 10 11 12 15 16 17 18 19 22 23 24 25 26 27 28 63 64 72 94 67 68 69 70
DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 POSLIM1 NEGLIM1 AXISIN1 AXISOUT1 QUADA1 QUADB1 ~INDEX1 ~HOME1
~RS VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 N/C ~RAMSLCT ~PERIPHSLCT R/~W ~STROBE ~WRITEENBL W/~R
C
~HOSTINTRPT DIRECTION1 PULSE1 ATREST1
D[0..15]
A[0..14]
U2 U2 1 ISR/W 2 3 4 1 PGR-
B
B
3 8 14 20 29 37 46 56 59 61 71 92 104 113 120
CP2N11 GND
A
A
PERFORMANCE MOTION DEVICES 55 OLD BEDFORD RD LINCOLN, MA 01773 Title RAM INTERFACE Size B Date:
8 7 6 5 4 3
Document Number Saturday, December 07, 2002
2
Rev B Sheet 1 of
1
0
7.5
User-defined I/O
The interface between the MC3510 chip and 16 bits of user output and 16 bits of user input is shown in the following figure. Comments on Schematic The schematic implements 1 word of user output registered in the 74LS377's and 1 word of user inputs read via the 244's. The schematic decodes the low 3 bits of the address to 8 possible UIO addresses UIO0 through UIO7. Registers and buffers are shown for only UIO0, but the implementation shown may be easily extended. The lower 8 address bits may be decoded to provide up to 256 user output words and 256 user input words of 16 bits.
MC3510 Technical Specifications 68
8
7
6
5
4
3
2
1
D[0..15]
A[0..14]
D
R? VCC 35 2 7 13 21 36 40 47 50 52 60 62 93 103 121 22K U2 U? U2 110 111 112 114 115 116 117 118 119 122 123 124 125 126 127 128 131 129 130 4 6 1 132 98 105 106 107 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 D0 D1 D2 D3 D4 D5 D6 D7 WEUIO0 3 4 7 8 13 14 17 18 11 1 D1 D2 D3 D4 D5 D6 D7 D8 CLK G 74LS377 USER OUTPUTS Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 2 5 6 9 12 15 16 19 UO0-0 UO0-1 UO0-2 UO0-3 UO0-4 UO0-5 UO0-6 UO0-7 A0 A1 A2 UIO A3 A4 1 2 3 6 4 5 A B C G1 G2A G2B 138 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 15 14 13 12 11 10 9 7 UIO0 UIO1 UIO2 UIO3 UIO4 UIO5 UIO6 UIO7
D
C
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
9 10 11 12 15 16 17 18 19 22 23 24 25 26 27 28 63 64 72 94 67 68 69 70
DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 POSLIM1 NEGLIM1 AXISIN1 AXISOUT1 QUADA1 QUADB1 ~INDEX1 ~HOME1
~RS VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 N/C ~RAMSLCT ~PERIPHSLCT R/~W ~STROBE ~WRITEENBL W/~R
U2 U2 ISWEW/R D8 D9 D10 D11 D12 D13 D14 D15 WEUIO0 3 4 7 8 13 14 17 18 11 1 D1 D2 D3 D4 D5 D6 D7 D8 CLK G 74LS377 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 2 5 6 9 12 15 16 19 UO0-8 UO0-9 UO0-10 UO0-11 UO0-12 UO0-13 UO0-14 UO0-15 A12 2 NOT NOR2 1 A12n IS2 1 3 UIO U2
C
~HOSTINTRPT DIRECTION1 PULSE1 ATREST1
U2 A12n IS2 1 3 OR2 OR3 UIOn W/R UIO0 2 3 4 U2 1 UI0n
SRLRCV SRLXMT SRLENABLE I/OINTRPT PRLENABLE
B
43 44 99 53 65 74 89 75 88 76 83 77 82 84 85 86 87
U2 D0 D1 D2 D3 D4 D5 D6 D7 18 16 14 12 9 7 5 3 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1G 2G 244 U2 D8 D9 D10 D11 D12 D13 D14 D15 18 16 14 12 9 7 5 3 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1G 2G 244 2 4 6 8 11 13 15 17 1 19 UI0-8 UI0-9 UI0-10 UI0-11 UI0-12 UI0-13 UI0-14 UI0-15 UI0n UI0n 2 4 6 8 11 13 15 17 1 19 UI0-0 UI0-1 UI0-2 UI0-3 UI0-4 UI0-5 UI0-6 UI0-7 UI0n UI0n USER INPUTS
THE LOGIC LABELED U2 MAY BE IMPLEMENTED IN A CPLD. THE LOWER 8 ADDRESS BITS, A0-A8, MAY BE DECODED TO PROVIDE 256 16 BIT USER INPUTS AND 256 USER OUTPUTS.
B
ANALOG1 ANALOG2 ANALOG3 ANALOG4 ANALOG5 ANALOG6 ANALOG7 ANALOG8 ANALOGVCC ANALOGREFHIGH ANALOGREFLOW ANALOGGND RSCLK 41 58 ~RESET CLOCKIN
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND CP2N11 GND
A
3 8 14 20 29 37 46 56 59 61 71 92 104 113 120
A
PERFORMANCE MOTION DEVICES 55 OLD BEDFORD RD LINCOLN, MA 01773 Title USER I/O Size B Date:
8 7 6 5 4 3
Document Number Saturday, December 07, 2002
2
Rev D Sheet 1 of
1
0
7.6
12-bit A/D Interface
The following schematic shows a typical interface circuit between the MC3510 and a quad 12 bit 2's complement A/D converter used as a position input device. Any single channel A/D can also be used provided it meets the interface timing requirements. Comments on Schematic The A/D converter samples the 2's complement digital words. DACRD- is used to perform the read and is also used to load the counter to FFh. The counter will be reloaded for each read and will not count significantly between reads. The counter will therefore start counting down after the last read and will generate the cvt- pulse after 12.75 sec. The conversions will take approximately 35 sec, and the data will be available for the next set of reads after 50 sec. The 12 bit words from the A/D are extended to 16 bits with the 74LS244.
MC3510 Technical Specifications 70
8
7
6
5
4
3
2
1
R? VCC DS[0..15] 35 2 7 13 21 36 40 47 50 52 60 62 93 103 121 22K A[0..15] U1 3 110 111 112 114 115 116 117 118 119 122 123 124 125 126 127 128 131 129 130 4 6 1 132 98 105 106 107 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 ISSTRBW/R A11 2 NOT U2 1 4 5 OR4 8 9 U? 10 11 12 13 15 16 17 18 19 20 21 22 4 AD7874 DS11 DS10 DS11 DS9 DS8 DS7 DS6 DS5 DS4 DS3 DS2 DS1 DS0 NOTE:SIGN EXTENTION FOR 2'S COMPLEMENT DACRD2 4 6 8 11 13 15 17 1 19 U2 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1G 2G 74LS244 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 18 16 14 12 9 7 5 3 DS15 DS14 DS13 DS12
D
VCC
DS[0..15]
~RS VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
VDD
D
DS0 DS1 DS2 DS3 DS4 DS5 DS6 DS7 DS8 DS9 DS10 DS11 DS12 DS13 DS14 DS15
9 10 11 12 15 16 17 18 19 22 23 24 25 26 27 28 63 64 72 94 67 68 69 70
DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 POSLIM1 NEGLIM1 AXISIN1 AXISOUT1 QUADA1 QUADB1 ~INDEX1 ~HOME1
ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 N/C ~RAMSLCT ~PERIPHSLCT R/~W ~STROBE ~WRITEENBL W/~R
POS1 POS2 NOTE:FS INPUTS ARE +- 10V POS3 POS4 CVTDACRDU2 1
1 2 27 28 5 6 7
VIN1 VIN2
VDD
DB11 DB10 DB9
VIN3 VIN4
DB8 DB7 DB6
CONVST RD CS REFIN
DB5 DB4 DB3 DB2 DB1
2 3
24 25
REFOUT DB0 DGND AGND CLK VSS INT
~HOSTINTRPT DIRECTION1 PULSE1 ATREST1
26
23
14
C
C
-5VA SRLRCV SRLXMT SRLENABLE I/OINTRPT PRLENABLE ANALOG1 ANALOG2 ANALOG3 ANALOG4 ANALOG5 ANALOG6 ANALOG7 ANALOG8 ANALOGVCC ANALOGREFHIGH ANALOGREFLOW ANALOGGND 43 44 99 53 65 74 89 75 88 76 83 77 82 84 85 86 87 CLK DACRDGND ENCNTVCC U2 3 4 5 6 2 9 1 10 7 A B C D CLK LOAD U/D ENT ENP 74ALS169 QA QB QC QD RCO 14 13 12 11 15 CLK DACRDGND 3 4 5 6 2 9 1 10 7 VCC U2 A B C D CLK LOAD U/D ENT ENP 74ALS169 QA QB QC QD RCO 14 13 12 11 15 U2 CVT2 NOT CLK 1
GND AGND
U2 DFF2 2 3 D CLK CL Q 1 ENCNT-
B
RSCLK
41 58
CLOCKIN
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
~RESET
DACRD- WILL LOAD THE COUNTER TO 255. 12.8 USEC. AFTER THE LAST DACRDTHE COUNTER WILL REACH 0 AND START THE NEXT CONVERSION. THE INPUT WILL BE CONVERTED IN 35 USEC. READY FOR THE NEXT READ 50 USEC LATER.
DACRDB
3 8 14 20 29 37 46 56 59 61 71 92 104 113 120
CP2N11 GND
NOTE:THE LOGIC LABELED U2 MAY BE IMPLEMENTEDIN A PLD.
A
4
A
PERFORMANCE MOTION DEVICES 55 OLD BEDFORD RD LINCOLN, MA 01773 Title 12 BIT A/D IN Size B Date:
8 7 6 5 4 3
Document Number Saturday, December 07, 2002
2
Rev A Sheet 1 of
1
0
7.7
16-bit A/D Input
The interface between the MC3510 chip and a 16-bit A/D converter as a parallel input position device is shown in the following figure. Comments on Schematic The schematic shows a 16 bit A/D used to provide parallel position input to axis 1. The 374 registers are required on the output of the A/D converters to make the 68-nanosecond access time of the CP. The worst-case timing of the A/D's specify 83 nanoseconds for data on the bus and 83 nanoseconds from data to tri-state on the bus. Each time the data is read the 169 counter is set to 703 decimal. This provides a 35.2-microsecond delay before the next conversion. With a 10microsecond conversion time the data will be available for the next set of reads after 50 microseconds. The delay is used to provide a position sample close to the actual position.
MC3510 Technical Specifications 72
8
7
6
5
4
3
2
1
R? VCC +5A DS[0..15] 35 2 7 13 21 36 40 47 50 52 60 62 93 103 121 22K A[0..15] U1 27 110 111 112 114 115 116 117 118 119 122 123 124 125 126 127 128 131 129 130 4 6 1 132 98 U2 105 106 107 A11 2 NOT BE IMPLEMENTEDIN A PLD. SRLRCV SRLXMT SRLENABLE I/OINTRPT PRLENABLE ANALOG1 ANALOG2 ANALOG3 ANALOG4 ANALOG5 ANALOG6 ANALOG7 ANALOG8 ANALOGVCC ANALOGREFHIGH ANALOGREFLOW ANALOGGND RSCLK 41 58 ~RESET CLOCKIN 43 44 99 53 65 74 89 75 88 76 83 77 82 84 85 86 87 1 A11n NOTE:THE LOGIC LABELED U2 MAY AGND
C
DS[0..15] VCC 3 4 7 8 13 14 17 18 1 11 U2 D0 D1 D2 D3 D4 D5 D6 D7 OC CLK 374 U2 3 4 7 8 13 14 17 18 1 11 DACRDD0 D1 D2 D3 D4 D5 D6 D7 OC CLK 374 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19
D
~RS VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
D
ISSTRBW/R A11n
2 3 4 5
U2 1 OR4 DACRDC1 2.2UF C1 2.2UF
BYTE
AGND1 AGND2 DGND
DS0 DS1 DS2 DS3 DS4 DS5 DS6 DS7 DS8 DS9 DS10 DS11 DS12 DS13 DS14 DS15
9 10 11 12 15 16 17 18 19 22 23 24 25 26 27 28 63 64 72 94 67 68 69 70
DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 POSLIM1 NEGLIM1 AXISIN1 AXISOUT1 QUADA1 QUADB1 ~INDEX1 ~HOME1
ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 N/C ~RAMSLCT ~PERIPHSLCT R/~W ~STROBE ~WRITEENBL W/~R
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
VANA
VCC
NOTE:FS INPUTS ARE +- 10V
28
U3 6 7 8 9 10 11 12 13 15 16 17 18 19 20 21 22 26 AD976
R1 AIN1 200 R2 33.2 3 4 25 CVTGND 24 23 REF CAP CS R/C 1 VIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BUSY
~HOSTINTRPT DIRECTION1 PULSE1 ATREST1
2 5 14 GND
C
SEE ANALOG DEVICES SPECIFICATIONS FOR ADITIONAL INFORMATION AND POWER BYPASSING.
B
B
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND CP2N11 GND VCC
VCC U2 3 4 5 6 CLK DACRDGND ENCNT2 9 1 10 7 A B C D CLK LOAD U/D ENT ENP 74ALS169 QA QB QC QD RCO 14 13 12 11 15
3 8 14 20 29 37 46 56 59 61 71 92 104 113 120
VCC U2 3 4 5 6 A B C D CLK LOAD U/D ENT ENP 74ALS169 QA QB QC QD RCO 14 13 12 11 15 3 4 5 6 2 9 1 10 7 U2 A B C D CLK LOAD U/D ENT ENP 74ALS169 QA QB QC QD RCO 14 13 12 11 15 CVT2
U2 1 NOT CLK 2 3
U2 DFF2 D CLK PERFORMANCE MOTION DEVICES 55 OLD BEDFORD RD LINCOLN, MA 01773 DACRD- WILL LOAD THE COUNTER TO 700. 38.4 USEC. AFTER THE DACRDTHE COUNTER WILL REACH 0 AND START THE NEXT CONVERSION. THE INPUT WILL BE CONVERTED IN 10 USEC. READY FOR THE NEXT READ AFTER 50 USEC. Title 16 BIT A/D INPUT Size B Date:
3
Q
1
ENCNTA
A
GND CLK DACRDGND
CLK DACRDGND
2 9 1 10 7
DACRD-
4
CL
Document Number Saturday, December 07, 2002
2
Rev A Sheet 1 of
1
1
8
7
6
5
4
7.8
External Gating Logic Index
A typical circuit for gating the Index signal with the encoder A & B channels is shown in the following schematic. Comments on Schematic In order for proper operation of the Index signal when used for position capture or phase correction, the signal must be gated with the A & B encoder channels to ensure that this signal is only active when all three signals are LOW. The motion processor does not perform this gating internally.
MC3510 Technical Specifications 74
5
4
3
2
1
D
D
R? VCC 35 2 7 13 21 36 40 47 50 52 60 62 93 103 121 22K
U1 110 111 112 114 115 116 117 118 119 122 123 124 125 126 127 128 131 129 130 4 6 1 132 98 105 106 107
C
9 10 11 12 15 16 17 18 19 22 23 24 25 26 27 28 63 64 72 94 QUADA1 QUADB1 HOME1 67 68 69 70
DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 POSLIM1 NEGLIM1 AXISIN1 AXISOUT1 QUADA1 QUADB1 ~INDEX1 ~HOME1
~RS VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 N/C ~RAMSLCT ~PERIPHSLCT R/~W ~STROBE ~WRITEENBL W/~R
C
~HOSTINTRPT DIRECTION1 PULSE1 ATREST1
SRLRCV SRLXMT SRLENABLE U3 2 3 4 OR3 1 INDX1 ANALOG1 ANALOG2 ANALOG3 ANALOG4 ANALOG5 ANALOG6 ANALOG7 ANALOG8 ANALOGVCC ANALOGREFHIGH ANALOGREFLOW ANALOGGND 41 58 ~RESET CLOCKIN I/OINTRPT PRLENABLE
43 44 99 53 65
B
B
QUADA1 QUADB1 INDEX1
74 89 75 88 76 83 77 82 84 85 86 87
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND CP24N11 GND PERFORMANCE MOTION DEVICES 55 OLD BEDFORD RD LINCOLN, MA 01773 Title EXTERNAL GATING LOGIC INDEX Size B Date: Document Number Saturday, December 07, 2002 Sheet
1 A
A
3 8 14 20 29 37 46 56 59 61 71 92 104 113 120
Rev A 1 of 1
5
4
3
2

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